1. Introduction
The ST67W611M1 module has a built-in SPI interface for short-range communication. The SPI interface is used in mission mode for control and data exchanges between the module and the host. Selection is done following the bootstrap configuration as described in the BOOT section.
The SPI bus is configured in full-duplex slave mode with 5 signals mapped on 5 dedicated module pins:
- SPI_CS (24) pin: Input. Chip select signal from the SPI master/host to the module
- SPI_CLK (28) pin: Input. SPI clock generated by the SPI master/host
- SPI_MOSI (27) pin: Input. SPI data from the SPI master/host to the module
- SPI_MISO (29) pin: Output. SPI data from the module to the SPI master/host
- SPI_RDY (21) pin: Output. SPI ready signal from the module to the SPI master/host
Note that the SPI_CS (24) pin can be used to convey a wake-up signal from the host. Refer to the wake-up section for more details.
2. SPI functional description and timings specification
SPI_CS and SPY_RDY are two control signals which are used to ensure a correct SPI data transfer:
- When the SPI master/host has data to transfer, it raises SPI_CS and waits for the slave ST67W611M1 module readiness, which is indicated by SPI_RDY signal/interrupt. Once SPI_RDY is raised by the module, the master enables SPI_CLK and send/receives the data on SPI_MOSI and SPI_MISO. The host stops SPI_CLK and lowers SPI_CS when the transfer is completed.
- When the slave ST67W611M1 module has data to transfer, it raises SPI_RDY signal/interrupt to inform the SPI master, which in turn raises SPI_CS and enables SPI_CLK in order to receive the data on SPI_MISO and send data on SPI_MOSI, if any. The master stops SPI_CLK and lowers SPI_CS when the transfer is completed.
The image and table below show the timing relationship between SPI_CLK, SPI_MISO and SPI_MOSI.
| Symbol | Description | Min | Max | Unit |
|---|---|---|---|---|
| Tcyc | SPI_CLK clock period | 251 | - | ns |
| Ts | MOSI setup time | 6 | - | ns |
| Th | MOSI hold time | 6 | - | ns |
| Tvld | MISO output delay | - | 8 | ns |
1 This means a maximum frequency of 40 MHz.
In the X-CUBE-ST67W61 software package, the SPI master's main configuration is as follows:
- Data size = 8 bits
- POL = 0
- PHA = 0
- First bit = MSB
3. SPI hardware implementation
The module's SPI pins must be connected to the host's corresponding SPI pins. Three aspects must be kept in mind while routing the SPI signals:
- Signal integrity: It is recommended to route these tracks with impedance control targeting 50 Ohms and care must be taken when changing layers. Also, it is advised to use coplanar routing (i.e. to separate these signals with ground) in order to avoid coupling. SPI signals must be routed far away from sensitive or noisy signals such as RF signals or power supply sources.
- SPI maximum frequency: The SPI clock maximum frequency is specified at 40 MHz. To reach this frequency, integrators must keep SPI_CLK, SPI_MOSI and SPI_MOSI tracks as short as possible on their boards in order to reduce the propagation delay and hence the skew between SPI_MISO and SPI_CLK at the host side. In all cases, customers should check the module's and host's SPI specifications.
- EMC: SPI signals routing and board layout must ensure that EMC certification tests pass. On a four-layer board, it is recommended to route them on inner layers to prevent SPI_CLK radiation. On a different board stack-up, it is recommended to run EMC simulations/measurements.
It is recommended to refer to ST's ST67W611M1 reference designs for implementation guidelines.