STM32WB Zigbee Hardware Setup

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1. STM32WB dual core

The STM32WB combines an Arm^® Cortex^®-M4 for the application, plus a 2.4 GHz radio subsystem and an Arm^® Cortex^®-M0+ processor running the firmware upgrade service (FUS) and the wireless stack .

STM32WB dual core

All the code running on Arm^® Cortex^®-M0+ (CPU2) is delivered as encrypted binary, and it is necessary to upgrade the wireless stack before developing a project on the application side.

Black box for customer perspective

All the code running on the Arm^® Cortex^®-M4 (CPU1) is delivered as source code.
The STM32WB is pre-loaded with root security system (FUS) firmware necessary to authenticate the selected wireless stack (binary encrypted format) loaded by the customer on st.com.

STM32WB memory mapping

Cortex^®-M0+ security protects the upper parts of the flash and SRAM2 memories. The sizes of the areas are automatically set during wireless stack install or update:

Secure flash start address (SFSA) is the lower boundary of protected flash memory. It is aligned on 4 Kbytes(WB5x) or 2 Kbytes(WB1x) granularity.
For STM32WB5x and STM32WB3x families:
- Secure backup RAM start address (SBRSA) and secure non-backup RAM start address (SNBRSA) are the lower address of protected parts of the SRAM2a and SRAM2b memories respectively. The size can be set with a granularity of 1 Kbytes.
- Backup SRAM2a can be used to store data when system is in standby mode.

2. System and Memory Overview

2.1. System Architecture

Here is a high-level overview of the system architecture:

CPU: The STM32WB features two Arm Cortex-M processors - a Cortex-M4 and a Cortex-M0+. The Cortex-M4 is the main processor and runs at up to 64 MHz, while the Cortex-M0+ is used for low-power tasks and runs at up to 32 MHz.
Memory: The STM32WB has up to 1 MB of Flash memory and up to 256 KB of SRAM. It also has a 32 KB backup SRAM, which can be used to store data even when the device is in low-power mode.
Radio: The STM32WB's radio subsystem supports both BLE 5.0 and IEEE 802.15.4 communication protocols.
Peripherals: The STM32WB has a wide range of peripherals, including timers, ADCs, DACs, SPI, I2C, UART, USB, and more. It also has a hardware encryption engine for secure data transmission.

2.2. Memory System

The memory organization of the STM32WB is designed to be flexible, efficient, and secure.

2.2.1. Flash Memory

Up to 1 Mbyte of flash memory single bank architecture:
Can be accessed starting from address 0x0000 0000 or 0x0800 0000 ( physical address)
4-Kbyte page granularity
Fast erase(22 ms)
Fast programming time (82 μs for double word)

The Flash memory is organized as follows:

Main memory block containing 256 pages of 4 Kbytes. Each page is made of 8 rows of 512 bytes.
Information block containing ST bootloader (system memory), user data (OTP) and option bytes for user configuration.

2.2.2. SRAM Memory

Internal SRAM1 (up to 192 KB).
Internal SRAM2a (32 KB) + SRAM2b (32 KB).

3. Radio System

The radio system in the STM32WB is a key feature of the microcontroller, as it enables wireless communication using Bluetooth Low Energy (BLE) and IEEE 802.15.4 protocols.
The radio system in the STM32WB includes a 2.4 GHz RF front end and a Bluetooth Low Energy (BLE) and IEEE 802.15.4 physical layer controller. The radio system is controlled from the CPU2, which contains the radio lower protocol software layers.

4. General-purpose I/Os (GPIOs)

The GPIO pins on the STM32WB can be configured in a variety of modes, including input, output, alternate function, and analog mode. The pin mode can be set using the device's registers.
More information can be found in GPIO wiki page.

5. USART/UART

The USARTs in the STM32WB support both synchronous and asynchronous communication modes, allowing them to communicate with a wide range of devices.
USART main features:

Full-duplex asynchronous communication
Two internal FIFOs for transmit and receive data
Synchronous master/slave mode and clock output/input for synchronous communications

USART signals: USART bidirectional communications require a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX):

6. IPCC

IPCC stands for Inter-Processor Communication Controller, which is a communication interface available on the STM32WB microcontroller. The IPCC is used to enable communication between the Cortex-M4 and Cortex-M0+.
It provides six bidirectional channels:

Six channels in the direction from processor 1 to processor 2
Six channels in the opposite direction

In a Zigbee application, the IPCC can be used to enable communication between the Zigbee protocol stack running on the Cortex-M4 processor and the application running on the Cortex-M0+ processor.

7. STM32WB Development ecosystem

The STM32WB55 Nucleo pack, STM32WB Nucleo boards and STM32WB discovery board combined with the STM32Cube ecosystem offer hardware and software tools to easily start developing your application.

NUCLEO-WB5 boards allow you to explore different product configurations and a wide range of wireless applications.

Development Boards