Getting started with LPBAM

This article explains Low-power modes, and provides code examples.

1. Introduction to LPBAM

The LPBAM (low-power background autonomous mode) is an operating mode that allows peripherals to be functional and autonomous independently from the device power modes, down to Stop 2 mode, without any software running. The LPBAM subsystem can chain different operations thanks to DMA linked-list transfers. The DMA operations can be related to:

• Peripheral data transfer
• Peripheral reconfiguration

Using LPBAM optimizes automatically the consumption: The device can be in a low power mode down to Stop 2, without any need to wake up for managing peripheral operation, thus saving energy loss during device wakeup time and run operation.
The bus clock and kernel clocks of peripherals are distributed only when requested by the autonomous peripherals.

1.1. Smart Run Domain (SRD)

The STM32U5 is split into two domains: CPU domain (CD) and SmartRun domain (SRD) File:Architecture of power and clock domains.png

The SRD architecture relies on a DMA allowing autonomous operation during low-power modes down to Stop 2. This architecture also features a 32-bit AHB bus matrix that interconnects:

• two masters:

– the main AHB bus matrix
– LPDMA1 (low-power DMA featuring one master port)

• two slaves:

– AHB3 peripherals including AHB to APB bridge connected to APB3
– internal SRAM4

Information

The SRAM4 is the only SRAM that can be accessed by the LPDMA1.

1.2. Peripherals supporting LPBAM

The table below lists all peripherals that support LPBAM

Low-power mode	Peripherals
Stop 0 and Stop 1	ADC4, ADF1, DAC1, GPDMA1, LPDMA1, LPTIMx (x = 1 to 4), LPUART1, MDF1, I2Cx (x = 1 to 4), SPIx (x = 1 to 3), USARTx (x = 1 to 5)
Stop 2	ADC4, ADF1, DAC1, LPDMA1, LPTIM1, LPTIM3, LPUART1, I2C3, SPI3

3. References

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