STM32WB Zigbee Hardware Setup

1. STM32WB dual core

The STM32WB combines an Arm^® Cortex^®-M4 for the application, plus a 2.4 GHz radio subsystem and an Arm^® Cortex^®-M0+ processor running the firmware upgrade service (FUS) and the wireless stack .

STM32WB dual core

All the code running on Arm^® Cortex^®-M0+ (CPU2) is delivered as encrypted binary, and it is necessary to upgrade the wireless stack before developing a project on the application side.

• Black box for customer perspective

All the code running on the Arm^® Cortex^®-M4 (CPU1) is delivered as source code.
The STM32WB is pre-loaded with root security system (FUS) firmware necessary to authenticate the selected wireless stack (binary encrypted format) loaded by the customer on st.com.

STM32WB memory mapping

Cortex^®-M0+ security protects the upper parts of the flash and SRAM2 memories. The sizes of the areas are automatically set during wireless stack install or update:

• Secure flash start address (SFSA) is the lower boundary of protected flash memory. It is aligned on 4 Kbytes(WB5x) or 2 Kbytes(WB1x) granularity.
• For STM32WB5x and STM32WB3x families:
  • Secure backup RAM start address (SBRSA) and secure non-backup RAM start address (SNBRSA) are the lower address of protected parts of the SRAM2a and SRAM2b memories respectively. The size can be set with a granularity of 1 Kbytes.
  • Backup SRAM2a can be used to store data when system is in standby mode.

2. System and Memory Overview

2.1. System Architecture

Here is a high-level overview of the system architecture:

• CPU: The STM32WB features two Arm Cortex-M processors - a Cortex-M4 and a Cortex-M0+. The Cortex-M4 is the main processor and runs at up to 64 MHz, while the Cortex-M0+ is used for low-power tasks and runs at up to 32 MHz.
• Memory: The STM32WB has up to 1 MB of Flash memory and up to 256 KB of SRAM. It also has a 32 KB backup SRAM, which can be used to store data even when the device is in low-power mode.
• Radio: The STM32WB's radio subsystem supports both BLE 5.0 and IEEE 802.15.4 communication protocols.
• Peripherals: The STM32WB has a wide range of peripherals, including timers, ADCs, DACs, SPI, I2C, UART, USB, and more. It also has a hardware encryption engine for secure data transmission.

Datasheet is available here.

2.2. Memory System

The memory organization of the STM32WB is designed to be flexible, efficient, and secure.

2.2.1. Flash Memory

• Up to 1 Mbyte of flash memory single bank architecture:
  • STM32WB55xG: 1MB Flash
  • STM32WB55xE: 512KB Flash
  • STM32WB55xC: 256KB Flash
  • STM32WB50xG: 1MB Flash
• Can be accessed starting from address 0x0000 0000 or 0x0800 0000 ( physical address)
• 4-Kbyte page granularity
• Fast erase(22 ms)
• Fast programming time (82 μs for double word)

The Flash memory is organized as follows:

• Main memory block containing 256 pages of 4 Kbytes. Each page is made of 8 rows of 512 bytes.
• Information block containing ST bootloader (system memory), user data (OTP) and option bytes for user configuration.

2.2.2. SRAM Memory

• Internal SRAM1
  • STM32WB55xG: 192KB SRAM1 @ 0x2000 0000
  • STM32WB55xE: 192KB SRAM1 @ 0x2000 0000
  • STM32WB55xC: 64KB SRAM1 @ 0x2000 0000
  • STM32WB50xG: 64KB SRAM1 @ 0x2000 0000
• Internal SRAM2a (32 KB) + SRAM2b (32 KB) @ 0x2003 0000

3. Radio System

The radio system in the STM32WB is a key feature of the microcontroller, as it enables wireless communication using Bluetooth Low Energy (BLE) and IEEE 802.15.4 protocols.
The radio system consists of a transceiver, a balun, and a power amplifier, and is designed to provide reliable and efficient wireless communication with low power consumption.
The radio system in the STM32WB includes a 2.4 GHz RF front end and a Bluetooth Low Energy (BLE) and IEEE 802.15.4 physical layer controller. The radio system is controlled from the CPU2, which contains the radio lower protocol software layers.

4. General-purpose I/Os (GPIOs)

The GPIO pins on the STM32WB can be configured in a variety of modes, including input, output, alternate function, and analog mode. The pin mode can be set using the device's registers.
General information can be found in GPIO wiki page.

5. Communication interfaces

5.1. USART/UART

The USARTs in the STM32WB support both synchronous and asynchronous communication modes, allowing them to communicate with a wide range of devices.
USART main features:

• Full-duplex asynchronous communication
• Two internal FIFOs for transmit and receive data
• Synchronous master/slave mode and clock output/input for synchronous communications

USART signals: USART bidirectional communications require a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX):
On STM32WB, we have:

• 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)
• 1x LPUART (low power)

General information can be found in UART wiki page.

5.2. Other advanced communication interfaces

• 2x I2Cs (SMBus/PMBus)
• 2x SPIs up to 32 MHz
• 1x serial audio interface (SAI) with two channels and three PDMs
• 1x USB 2.0 FS device with embedded crystal-less oscillator, supporting BCD and LPM and one Quad-SPI with execute-in-place (XIP) capability.

6. IPCC

IPCC stands for Inter-Processor Communication Controller, which is a communication interface available on the STM32WB microcontroller. The IPCC is used to enable communication between the Cortex-M4 and Cortex-M0+.
It provides six full-duplex channels:

• Six channels in the direction from processor 1 to processor 2
• Six channels in the opposite direction

In a Zigbee application, the IPCC is used to enable communication between the Zigbee protocol stack running on the Cortex-M0+ processor and the application running on the Cortex-M4 processor.

7. Power supply management

The device is designed to be extremely low-power. The device integrate an SMPS step-down converter to improve low power performance when the V_DD voltage is high enough. The SMPS can also be switched on or set in bypass mode at any time by the application software.
The device has different voltage supplies:

• V_DD = 1.71 to 3.6 V: external power supply for I/Os and system functions such as RF, SMPS, reset, power management and internal clocks.
• V_DDA = 1.62 (ADC/COMPs) to 3.6 V: independent power supplies for analog input for ADC and comparators.
• V_DDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers.

STM32WB device supports several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wake-up sources.

It is up to the user to select one of these low-power modes:

• Sleep
• Low-power run
• Low-power sleep
• Stop 0, Stop 1 and Stop 2
• Standby
• Shutdown

Please refer to the datasheet section 3.7.5 for more details.

8. STM32WB Development ecosystem

The STM32WB is designed to be used with a variety of development boards, including the STM32WB55 Nucleo pack, the STM32WB Nucleo boards and the STM32WB discovery board.

Development Boards

9. ST-LINK USB cable connections for P-NUCLEO-WB55 and STM32WB5MM-DK Discovery kit boards

The USB cable from the PC is used to power and interact with the STM32:

• P-NUCLEO-WB55 : Jumper JP1 to USB STL and USB ST-LINK to be used
• STM32WB5MM-DK Discovery kit : Jumper JP2 to 1-2 and USB ST-LINK to be used

Nucleo	Discovery Kit

10. Log via UART

STM32WB platforms embed the ST-LINK/V2 in-circuit debugger and programmer for STM32 microcontrollers. The single-wire interface module (SWIM) and JTAG/serial wire debugging (SWD) interfaces are used to communicate with the STM32WB microcontroller. It also supports the STM32 virtual COM port driver for communication between a PC and the application processor via a serial interface.
Use any convenient software terminal to open the serial communication port of the PC to check the messages from the board. Select your serial port and set up your connection as follows (example done with Tera Term software). Set a new serial connection to the ST platform:

Tera Term setup (1/2)

Setup your serial connection as below:

Tera Term setup (2/2)