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1. Introduction
STM32WBA CubeFW provides low power features that are integrated into the application framework.
Once the low power is enabled in the application, the system framework is responsible of choosing the lowest possible power mode that can be used. Serval parameters are taken into account such as the application use case or the radio activity.
2. Concepts
2.1. Low power general overview
STM32WBA SoC low power mode is determined by both Link Layer operating modes and SoC PWR modes.
Details are given in the next sections.
2.1.1. Link Layer operating modes
Link Layer operating modes are detailed in the table below.
Operating mode | Purpose |
---|---|
Active – Standby | Link Layer is in active mode when the radio is operating. Standby is used on active waiting of radio event (BLE IFS, RX on IDLE for 802.15.4). |
Sleep | This mode is used when there is no radio activity. Baseband clock (active clock) has to be switched OFF. RXTX SRAM or sequence SRAM are not available. HW Link Layer registers are accessible as long as bus clock remains ON. |
Deep Sleep | Deep Sleep mode is the lowest low power mode for Link Layer IP. This mode is only available when the is no current/up-coming radio activity. Baseband clock (active clock) is switched OFF. All power domains are switched OFF except sleep timer one. Bus clock has to be ON for sleep timer registers access. |
Deep sleep mode entry/exit is time consuming. Therefore, the next radio activity has to be far enough to power down the radio.
A threshold value is available in system framework and can be configured as needed. See RADIO_DEEPSLEEP_WAKEUP_TIME_US
macro in system configuration.
2.1.2. SoC PWR power modes
STM32WBA SoC supports four main PWR power modes: run, sleep, stop and standby. Details are given below.
2.1.2.1. Run mode
The CPU and the system clock are running. It shall be used only when it is required to execute code.
2.1.2.2. Sleep mode
CPU clock is off (CPU stops fetching code), all peripherals including Cortex-M33 core such as NVIC and SysTick can run and wake up the CPU when an interrupt or an event occurs. This should be used when a peripheral (that does not have a kernel clock) requires the system clock to operate while the CPU is stopped.
2.1.2.3. Stop modes
Stop modes achieve the lowest power consumption while retaining the content of registers. The SRAM content can be selected to be retained or not. All clocks (except some autonomous peripherals bus and kernel clocks) in the Core domain are stopped (system clock, high-speed oscillators).
There are two stop modes:
- stop0: This is the stop mode available when a kernel clock is enabled or a autonomous peripherals bus clock is requested.
The 2.4GHz radio can still be active when in Stop 0 Range1. For this, the high-speed system clock and peripheral kernel clocks may be kept running. - stop1: Lowest stop mode available in WBA5x series where all bus and kernel clocks are off.
2.1.2.4. Standby modes
The Standby mode is used to achieve the lowest power consumption. The internal regulator is switched off so that the Core domain is powered off. High-speed oscillators are off too (PLL, HSE and HSI). The LSE or LSI can still run.
When entering Standby mode, register contents are lost except for registers in the Backup domain and Standby circuitry. Regarding peripherals, only RTC, TAMP, and WKUP are retained. Standby mode exit leads to a SoC reset.
The standby mode described above is Standby without retention.
Optionally, the user can retain the content of SRAMs. It is Standby with retention mode.
- the full SRAM1 and/or SRAM2 can be retained in Standby mode, supplied by the low-power regulator.
- the 2.4 GHz RADIO Sleep Timer, RXTXRAM and sequence SRAM can be retained in Standby mode, supplied by the low-power regulator.
2.2. Low power in Connectivity applications
2.2.1. Low power manager Utility (LPM)
2.2.1.1. LPM Utility
The low power manager provides a simple interface to receive the input from up to 32 different users and computes the lowest possible power mode the system can use. Each LPM client can request a disablement (or re-enablement after deactivation) for stop and standby modes when necessary. The API to use is:
UTIL_LPM_SetStopMode
for Stop mode.UTIL_LPM_SetOffMode
for Standby mode.
Low power Sleep mode is selected when Stop and Standby are disabled.
Users can obtain the low power mode that is going to be selected at that time with UTIL_LPM_GetMode
API.
2.2.1.2. Platform interfaces
Once it is time to enter in low power mode, application is responsible to call UTIL_LPM_EnterLowPower
. According to the lowest low power mode available, LPM Utility will call appropriate interface to enter Sleep, Stop or Standby mode at SoC level. Those interfaces has to be defined at application level (system side).
Low power platform interfaces are:
PWR_EnterSleepMode
andPWR_ExitSleepMode
for Sleep mode.PWR_EnterStopMode
andPWR_ExitStopMode
for Stop mode.PWR_EnterOffMode
andPWR_ExitOffMode
for Standby mode.
2.2.2. Low power Stop modes for Connectivity
Both stop0 and stop1 are supported. As a remainder:
- when Link Layer is in active/standby mode, SoC can achieve stop0.
- when Link Layer is in sleep mode, SoC can achieve stop1.
2.2.2.1. Low power Stop mode entry
Below is the mandatory system configuration before entering Stop modes (in order)
- ICache IP shall be disabled.
- FLASH latency: 3, SRAM1/2 latencies: 1.
- CPU shall be in deep sleep mode.
- PWR VOS shall be stable.
2.2.2.2. Low power Stop mode exit
At low power Stop mode exit, System Clock Manager (SCM) module is called to reconfigure the system clock as it was before entering low power.
See System Clock Manager for further information about this system module.
2.2.3. Low power Standby mode for Connectivity
2.2.3.1. Standby strategy
For Connectivity applications, the lowest low power mode achievable is Standby with retention. Indeed, the system has to retain
- Link Layer configuration and context: Link Layer dedicated SRAM retained.
- Application content: at least SRAM1 retained. If SRAM1 is not enough RAM for the application, SRAM2 shall be retained too.
As CPU is reset at standby exit, non-retained configuration (SRAMs content) shall be re-applied (e.g SoC register content). This concerns:
- NVIC interrupts, system and user/application related.
For system side, Link Layer high priority, Link Layer SW low priority, RCC, RTC interrupts are configured (priority) and enabled. - Link Layer peripheral clock (radio bus clock) is enabled.
- SoC IP are re-initialized completely (including related NVIC interrupts if handled by HAL SW).
- RTC peripheral clock. If RTC registers are retained as RTC IP is part of backup domain, peripheral clock is reset at Standby exit.
2.2.3.2. Save & restore mechanism
2.2.3.2.1. CPU context registers
Default behavior at standby exit - after CPU reset - is to execute reset handler code. For connectivity applications, the goal is to execute the low power standby exit procedure (PWR_ExitOffMode
function after __WFI
) as system does for Stop mode.
Hereafter is the description of the mechanism implemented in WBA5 solution.
- At Standby entry, system saves the CPU registers related to the execution context by calling
CPUcontextSave
. This concerns R4-R12, LR and SP general purpose registers that are backup in CPU stack. - Connectivity applications have a specific reset handler that restores CPU context registers from the CPU stack if system resets from standby exit.
- As a result, the next executed instruction is the one after
__WFI
inPWR_EnterOffMode
.
2.2.3.2.2. CPU peripherals registers
CPU peripheral registers are also maintained with backup_system_register
and restore_system_register
APIs.
Connectivity system backuped registers are SCB CPACR
(FPU related) and SysTick CTRL
/LOAD
/VAL
.
If the user has any other CPU peripheral register to backup, it can be added to register_backup_table
in System/Config/LowPower/user_low_power_config.c
.
/* Table of CPU peripheral registers to backup/restore when standby mode available */
const volatile uint32_t* const register_backup_table[] =
{
&(SCB->CPACR), /* FPU SCB->CPACR register */
&(SysTick->CTRL), /* SysTick CTRL register */
&(SysTick->LOAD), /* SysTick LOAD register */
&(SysTick->VAL), /* SysTick VAL register */
/* USER CODE BEGIN RBL */
/* USER CODE END RBL */
};
2.3. Low power concept summary
Here is a summary diagram of the STM32WBA5 low power features.
3. Interfaces
3.1. LPM Utility
scm_init |
---|
Description
|
scm_setsystemclock |
---|
Description
|
scm_setwaitstates |
---|
Description
|
scm_notifyradiostate |
---|
Description
|
3.2. Low power platform interfaces
3.3. CPU context save & restore
3.4. CPU peripherals save & restore
4. How to
TBD.