STM32CubeWBA: System Clock Manager

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Information

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1. Introduction

The system clock manager (SCM) is module responsible for managing CPU system clock source and frequency according to Connectivity purposes.
System clock manager module defines different users that can request different configurations. Modules determines which one is best to suit the system and all SCM users needs.

SCM module also steps in low power wake-up phase by applying usable configuration for RF activities.

2. Features

2.1. SCM users principle

The module is based on a client request mechanism. SCM defines users (up to 32) that can request a clock frequency modification.
There is a system user SCM_USER_LL_FW and multiple application users can be define in addition to existing SCM_USER_APP. All users has the same weight/priority.

Among all the requests, the system clock manager determines the one that fulfills all the needs. The best system clock evaluation is realized at each new request.

2.2. Supported configurations

2.2.1. Overview

Supported configurations are fixed. Unlike SCM users, it is not possible to add SCM configurations over existing ones.

Each SCM configuration is used for a particular purpose.
The table below presents all the supported configuration (increasing order of priority) and their use at system side.

Supported SCM configurations

SCM configuration	Purpose
HSE 16MHz	Nominal - no radio activity Requested in radio interrupt (ending radio event notification from link layer)
HSE 32MHz	Radio activity Requested in radio interrupt (starting radio event notification from link layer)
PLL	PLL is used for BLE audio use cases

Information

HSI as system clock source is not supported.

Information

The SCM always select the request with the most prior configuration (as needs with the lower ones are fulfilled).

2.2.2. Corresponding SoC configuration

In order to achieve these configurations, SCM module is responsible to adapt several SoC related parameters:

• Flash & SRAMs latencies.
• Flash & SRAMs wait states.
• Regulator supply output voltage (VOS).
• AHB5 divider.

They are presented per SCM configuration is the table below.

SCM related SoC parameters

SCM configuration	Flash & SRAMs latencies	Flash & SRAMs wait states	VOS	AHB5 divider
HSE 16MHz	Flash latency: 1 SRAM1/2 latencies: 1	Flash WS: 1 SRAM1/2 WS: 1	2	2
HSE 32MHz	Flash latency: 0 SRAM1/2 latencies: 0	Flash WS: 0 SRAM1/2 WS: 0	1	1
PLL	Flash latencies: 3 SRAM1/2 latency: 0	Flash WS: 0 SRAM1/2 WS: 0	1	1

2.3. PLL usage

PLL usage and configuration is defined as follow:

• PLL source is always HSE 32MHz.
• If there is one global PLL configuration for SCM, PLL parameters (PLL mode, PLL multiplier & dividers) can be adapted to user needs with dedicated interfaces.
  See PLL management interfaces section for more information.

2.4. Low power management

SCM module is used in low power management for both low power entry and exit.

• For low power mode entry (stop1 or standby), SCM interface scm_setwaitstates(LP) is used for adapting FLASH & SRAMs wait states and latencies.
• For low power mode exit (stop1 and standby), SCM interface scm_setup() is used for applying the system clock confirmation that were before low power entry. Regarding standby mod exit, PLL configuration is re-applied (even if not used at that time) as PLL registers has been reset.

2.5. SCM elected request execution

On one hand, decreasing clock speed is handled immediately.
On the other hand, increasing clock speed requires more time to setup (including oscillators to be enabled, propagation delays, PLL lock, ...). To guarantee system performances and radio activity timings, SCM implemented an interrupt based mechanism.

Indeed, when the system clock source has to be changed, the targeted oscillator (HSE or PLL) is enabled alongside dedicated RCC ready flag. The other part of system clock configuration is done in the RCC interrupts itself once clock is ready. This permits the firmware to keep running with the actual clock source and speed until targeted clock is ready.

There is two RCC interrupts the SCM handles:

• RCC HSE ready flag (raised just after low power mode exit as system clock is HSI 16MHz).
• RCC PLL ready flag (always raised when system clock is on HSE as HSE is PLL source clock).

2.6. SCM concept summary

Here is a summary diagram of SCM module.

File:SCM Overview.png

System Clock Manager concept summary

3. Interfaces

3.1. SCM users

The error codes for AMM are listed below:

SCM users

SCM user	Description
SCM_USER_LL_FW	XXX
SCM_USER_APP	XXX

3.2. SCM functions

3.2.1. General interfaces

scm_init
Description Initialize the System Clock Manager module. Syntax void scm_init(void); Parameters None Return Value None

scm_setsystemclock
Description Request system clock configuration (clock source & frequency) change. Syntax void scm_setsystemclock (scm_user_id_t user_id, scm_clockconfig_t sysclockconfig); Parameters [in] user_id Type: scm_user_id_t Description: SCM user that request the change [in] sysclockconfig Type: scm_clockconfig_t Description: SCM configuration requested Return Value None

scm_setwaitstates
Description Configure the Flash and SRAMs wait cycle (when required for system clock source change) Syntax void scm_setwaitstates(const scm_ws_lp_t ws_lp_config); Parameters [in] ws_lp_config Type: const scm_ws_lp_t Description: Flash and SRAMs wait cycle configuration Return Value None

scm_notifyradiostate
Description Notify the SCM the state of the Radio. Syntax void scm_notifyradiostate(const scm_radio_state_t radio_state); Parameters [in] radio_state Type: scm_radio_state_t Description: State of the radio (active or not active) Return Value None

3.2.2. Low power management

scm_setup
Description Setup the system clock source in usable configuration for Connectivity use cases. Called at startup or out of low power modes. Syntax void scm_setup(void); Parameters None Return Value None

scm_standbyexit
Description Restore system clock configuration when moving out of standby. Syntax void scm_standbyexit(void); Parameters None Return Value None

3.2.3. PLL management

scm_pll_setconfig
Description Configure the PLL mode and parameters before PLL selection as system clock. Syntax void scm_pll_setconfig(const scm_pll_config_t *p_pll_config); Parameters [in] p_pll_config Type: scm_pll_config_t Description: PLL coniguration to apply Return Value None

scm_pll_fractional_update
Description Configure the PLL for switching fractional parameters on the fly. Syntax void scm_pll_fractional_update(uint32_t pll_frac); Parameters [in] pll_frac Type: uint32_t Description: Up to date fractional configuration Return Value None

scm_pllconfigready
Description Called each time the PLL config is ready. Syntax void scm_pllconfigready(void); Parameters None Return Value None

3.2.4. RCC ISR handling

scm_hserdy_isr
Description SCM HSERDY interrupt hander. Switch system clock on HSE. Syntax void scm_hserdy_isr(void); Parameters None Return Value None

scm_pllrdy_isr
Description SCM PLLRDY interrupt hander. Switch system clock on PLL. Syntax void scm_pllrdy_isr(void); Parameters None Return Value None

4. How to

TBD.