STM32CubeWBA: System Clock Manager

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1. Introduction

The system clock manager (SCM) is module responsible for managing CPU system clock source and frequency according to Connectivity purposes.
System clock manager module defines different users that can request different configurations. Modules determines which one is best to suit the system and all SCM users needs.

SCM module also steps in low power wake-up phase by applying usable configuration for RF activities.

2. Features

2.1. SCM users principle

The module is based on a client request mechanism. SCM defines users (up to 32) that can request a clock frequency modification.
There is a system user SCM_USER_LL_FW and multiple application users can be define in addition to existing SCM_USER_APP. All users has the same weight/priority.

Among all the requests, the system clock manager determines the one that fulfills all the needs. The best system clock evaluation is realized at each new request.

2.2. Supported configurations

2.2.1. Overview

Supported configurations are fixed. Unlike SCM users, it is not possible to add SCM configurations over existing ones.

Each SCM configuration is used for a particular purpose.
The table below presents all the supported configuration (increasing order of priority) and their use at system side.

Supported SCM configurations
SCM configuration	Purpose
HSE 16MHz	Nominal - no radio activity Requested in radio interrupt (ending radio event notification from link layer)
HSE 32MHz	Radio activity Requested in radio interrupt (starting radio event notification from link layer)
PLL	PLL is used for BLE audio use cases

Information

HSI as system clock source is not supported.

Information

The SCM always select the request with the most prior configuration (as needs with the lower ones are fulfilled).

2.2.2. Corresponding SoC configuration

In order to achieve these configurations, SCM module is responsible to adapt several SoC related parameters:

Flash & SRAMs latencies.
Flash & SRAMs wait states.
Regulator supply output voltage (VOS).
AHB5 divider.

They are presented per SCM configuration is the table below.

SCM related SoC parameters
SCM configuration	Flash & SRAMs latencies	Flash & SRAMs wait states	VOS	AHB5 divider
HSE 16MHz	Flash latency: 1 SRAM1/2 latencies: 1	Flash WS: 1 SRAM1/2 WS: 1	2	2
HSE 32MHz	Flash latency: 0 SRAM1/2 latencies: 0	Flash WS: 0 SRAM1/2 WS: 0	1	1
PLL	Flash latencies: 3 SRAM1/2 latency: 0	Flash WS: 0 SRAM1/2 WS: 0	1	1

2.3. PLL usage

PLL usage and configuration is defined as follow:

PLL source is always HSE 32MHz.
If there is one global PLL configuration for SCM, PLL parameters (PLL mode, PLL multiplier & dividers) can be adapted to user needs with dedicated interfaces.
See Texte du lienfor more information.

2.4. Low power management

2.5. SCM elected request execution

On one hand, the decrease clock speed request is handled immediately.

On the other hand, the increase clock speed request requires more time to setup (including oscillators to be enabled, propagation delays, PLL lock, ...). To guarantee system performances and radio activity timings, SCM implemented an interrupt based mechanism.
Indeed, when the system clock source has to be changed, the targeted oscillator

This permits the firmware to keep running with the actual clock source and speed until the system is ready.

File:SCM Overview.png

System Clock Manager concept

3. Interfaces

TBD.

texte affiché du point d'ancrage

Ancre

4. How to

TBD.