Basics of power supply design for MCU

Introduction

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This article covers general aspects about designing power supplies for STM32 based applications. It provides general guidelines on important characteristics, how to choose components, and optional features related to power supplies.

The first part is about power supplies in general.

• Define main characteristics of power supplies and impacts on applications.
• Talk about types Switched mode power supply (SMPS) and low dropout regulator (LDO) and compare them.
• Provide important power management considerations.

The second part specifies STM32 requirements regarding power supplies (PS).

• Power architecture of STM32.
• STM32 specific requirements regarding power supplies.
• How to identify the requirements of the application.
• Included features in STM32.

1. General notions power supply

Power supply quality is fundamental for reliability of any electronic application. The purpose of this section is to get an overview of considerations about power supplies.

Ideally an electronic application should be supplied with a fixed voltage, response very fast to current calls and without any noise.

Applications are powered by an external source of electricity that can be a battery, a USB cable, or AC current for example. These sources can be noisy, especially if they supply power applications such as motors. Furthermore, the voltage can vary a lot, in the case of batteries depending on the charge and loading current.

Example of application with power source/supplies and loads

The role of the power supply is to generate a steady supply voltage for the application, independent from the input voltage and output current variations. In this document a difference is made between power source and power supply.

• Application: Scope of the engineering process.
• Power source: External energy source given with certain characteristics. Outside of the application.
• Power supply: System that converts voltage from power source to the load that must match power source and load characteristics. Inside the application.
• Load: Every component that consumes current from the power supply.

For more information about supplies topology for a wide variety of applications and components references see this guide: Power management guide Power management guide

As current exists in two major forms, Alternative (AC) and Continuous (DC) power supplies are categorized by their type of conversion AC/DC, DC/DC, DC/AC (invertor) and AC/AC. In this topic we will only cover DC/DC supplies.

1.1. General definitions

illustrating voltage current notions

1.1.1. Voltage

Input Voltage

Power supplies are designed to handle a range of input voltage, see operating voltage in datasheet electrical characteristic table. If voltage spikes from the power source exceed this limit, it could lead to destruction of the power supply, and the whole application. Chosen component must handle highest voltage spikes and not only the average voltage. Even short spikes can damage components.

Output Voltage

The loads datasheet provides a range of operating voltage. The load might not work properly if applying insufficient voltage, on the other hand exceeding maximum value may lead to irreversible damage. Nominal output voltage must match operating voltage of loads.
Transients are also to be considered. Dips are short drops of voltage. Swells are the inverse; it is short overshoot of the voltage level. These phenomena can occur while load current transient phases or input voltage transient phases. Various aspects are covered in different sections of this wiki: Noise, Power management.

1.1.2. Current

current consumption characteristics

Max continuous current

Max continuous current corresponds to the consumption of the load in the worst-case scenario. The power supply must be able to provide this much current continuously. This gives the minimum requirement for the power supply max continuous current.

Peak current

Peak currents are short time current spikes that occur in transient phases like power up, clock frequency shifting, high load I/O switching.

Inrush current

In addition, the circuit contains capacitors. At power up these capacitors draws a huge amount of current to charge, this must be handled by the power supply.

Average current

Average current is helpful to estimate energy consumption and size finite or limited power source, like battery, to guarantee lifetime. It is also possible to have a power supply that only delivers the average current and use local electricity storage like capacitors to absorb transient currents.

Quiescent current (IQ)

Quiescent current, I_Q, is the consumption of the power supply itself. This may be negligible with medium or high currents but becomes significant in low power applications.

1.1.3. Noise

This section only talks about noise as choosing criteria for supply, refer to section Power management Decoupling to get more information about noise in general and good practice.
Some applications are especially sensitive to noise like precision analogue devices or high frequency digital ICs. There are different notions related to noise regarding power supply:

Intrinsic noise

Physical properties of transistors and resistors implies noise. This source of noise is independent of input, it is generated by the regulator itself, in particular the retroaction loop.

Switching ripple (SMPS)

In SMPS Power supply SMPS, the voltage regulation is done by switching a transistor at high-speed rate (~50kHz-2MHz), this induces voltage variation on output. The amplitude of the ripple mainly depends on the size of the inductance, the output capacitor and output current. This constitutes the main disadvantage of SMPS.

Power-Supply Rejection Ratio (PSRR)

PSRR is the ability of the power supply to reject input noise, coming from the power source. It's like the power supply acts as a filter. PSRR value is often given in datasheets. This is an important characteristic for low noise applications.

1.1.4. Efficiency

Power supply efficiency is an important factor in power consumption. In many cases energy is a limited or expensive resource. In ultra-low power applications, running on battery or induced current (RFID), efficiency is key to ensure high lifetime. In high power application, power loss represents a significative amount of energy and a cost.
Furthermore, energy losses are dissipated in heat. If losses are concentrated in a small area, components may heat a lot and cause reliability issues.
Power supplies datasheets provide typical efficiency characteristics (In the case of LDO this is a bit different, look at relative section).

1.2. Types of power supply

In DC/DC conversion, there are two major methods, linear regulator and SMPS (Switching Mode Power Supply).

LDO Implementation schematic example, STLQ020

1.2.1. Low Drop output (LDO)

Linear regulators are a low cost and easy way to regulate voltage. These are only step-down regulations with a minimal drop voltage, $V_{out}\leq V_{in}-V_{dropmin}$.
Low dropout regulators, LDO, are linear regulators with a low Vdrop, about 100mV-500mV, which allow output voltage very close to the input voltage.
The regulator itself doesn't introduce much noise relatively from SMPS. Thanks to that, LDOs are preferred for low noise application. These are characterized by their intrinsics noise and PSRR.
These types of power supplies are generally fully integrated and only require few simple components like resistor or capacitor.
To regulate output voltage, LDO dissipates the difference in heat. $P_{dissipated}=(V_{in}-V_{out})*I$. The major drawback is efficiency, $\alpha \simeq {V_{out} \over V_{in}}$(true for negligible quiescent current $I_{Q}\ll I_{out}$), especially when the difference between Vin and Vout is huge. Because of that they are not recommended for 1 amp or higher current applications. Otherwise make sure to have proper thermal dissipation.
Note: in low current application quiescent current, IQ, of the LDO might become significative: $\alpha \simeq {(V_{out}*I_{out}) \over (V_{in}*I_{in})};I_{in}=I_{out}+I_{Q}$
Note: Input current is equal to output current plus the quiescent current, current consumed by the LDO itself. The input current is not influenced by the voltage drop as LDO dissipates this drop in heat.

1.2.2. SMPS

Example of output ripple buck SMPS

L7983 SMPS Efficiency example

Switching Mode Power Supplies are the most efficient way to regulate voltage, often between 80% and 90% up to 95% of efficiency for the best.
They are composed of switches, transistors, and diodes, that chop the current and a strong L/C filter that convert chopped to continuous current and voltage.
There are different topologies of SMPS, the most common is step-down Buck regulator.

Simplified synchronous Buck converter schematic

The switching transistors generate ripple which is basically noise on Vout.
Note: PSRR is not relevant concerning SMPS
Note: There are low noise SMPS that are designed to have small ripples, but they have lower efficiency.

These types of power supplies are generally more expensive and take more place on PCB. It requires higher values capacitors and an inductor.

SMPS Implementation schematic example, L7983

SMPS are efficient in a certain range of power, so an over dimensioned SMPS is not only more expensive but also less efficient.

Note: Input current is equal to $I_{in}={V_{out} \over V_{in}}*{I_{out} \over \alpha }$ plus the current consumed by the SMPS itself. The input current is smaller when the voltage drop is higher as the SMPS converts power with minimal dissipation.
Note: As SMPS requires more decoupling capacitors, the inrush current is bigger.

1.2.3. Comparing SMPS/LDO

SMPS are more efficient than LDO, especially with important input/output voltage difference.
LDO are low cost and easy to implement, where SMPS requires a coil and more space on PCB.
LDO generates less noise than SMPS.
High PSRR LDO can be used on the output of a SMPS to reduce switching noise while achieving good efficiency.

1.3. Power management

1.3.1. Decoupling

To provide a steady voltage without variations and noise, decoupling is a key element power supply design. Supply voltage variations are introduced by load(current) variations and power conversion (LDO/SMPS…).

coil voltage drop

• Load current transient: Digital IC, motor control, communication IC, and most of loads induce current variations. Any conductor has parasitic resistance and inductance that oppose to current variations. This results in voltage drop/peak across power lines. See illustrated below voltage drop induces by current variation in an inductance:
• Not perfect power supplies regulation: The active regulation as a latency to current variations. The retroactive loop introduces noise by measurement errors. In the case of SMPS there is also the ripple due to switching, see Noise section for more details.
• Power source: The third thing to consider is that the power source itself can be noisy for some reasons that are often imposed. Filtering can be required.

Decoupling/Bypass capacitors

Decoupling consists of placing energy storage on different nodes of the power supply grid to locally supply these transient currents. These energy storages are capacitors placed as close as possible to transient generating circuits. The goal is to minimize the size of current loops to minimize parasitic resistors and inductance.

Schematic line inductance + decoupling

Frequency response line inductance + decoupling

Figure above shows frequency response with different decoupling capacitor. Serial coils amplify high frequencies, decoupling capacitor cuts this amplification, the drawback is resonance frequency.

Capacitor equivalent model

The second trouble is equivalent serial inductance (ESL). Components have parasitic inductances capacitance and resistance. The figure represents a common realistic capacitor model, in the case of decoupling we will focus on ESL. Capacitor ESL depends mainly on technology and package type and size. See on the figure below, that decoupling capacitors filter medium frequencies, but ESL effect takes over at high frequencies.

Frequency response line inductance + decoupling + ESL

As bigger capacitors have higher ESL due to bigger package, it is recommended to mix different size of capacitors to cover the widest band as shown in Figure below. Furthermore, placing multiple capacitors in parallel reduces equivalent serial inductance as $L1//L1={L1*L1 \over L1+L1}={L1 \over 2}$ .

Schematic combined capacitor decoupling

Frequency response combined capacitor decoupling

For digital ICs like MCU, put a capacitor as close as possible of each V_DD/Vss pin pair. If V_DD pins are not close to Vss pins, put the capacitor close to V_DD and directly to the ground plan.

Short current loop; ST, AN5307 Rev 6; 2022, p 32

It is important to select low ESR/ESL capacitors (equivalent serial resistance/inductance). Especially use ceramic SMD with the smallest package for a given capacitance. A bigger package has bigger ESL and ESR.

Bulk capacitors

Bulk capacitors provide energy to the system to prevent voltage drops, they are generally big capacitance and placed around the power supply.
In fact, the difference between decoupling, bypass and bulk capacitor is not neat, all are used to stabilize voltage. Roughly bulk capacitors have bigger capacitance and provide more current for a longer period (filter lower frequencies).

In addition, for power supplies, these capacitors play two others major roles:

• Filter noise from the power supply itself, especially ripple from SMPS, and noise replicated from the power source.
• Power supply has feedback loops regulations that need capacitors to remain stable and accurate.

It is mandatory to respect capacitors values given in datasheets.

In conclusion capacitors play important roles in supply path. It is important to pay attention to decoupling and PCB layout. Due to parasitic inductances in lines and capacitors and variety of frequencies to filter, one big capacitor is not equivalent to properly sized one's placed at different places of the circuit. Each component datasheet provides recommendations including application reference schematics.

1.3.2. Power on sequence

The power on sequence is the phase while the voltage is rising, and components power on. The application is often composed of multiple ICs which might have different startup voltage and delays. It is a good option to have a quick voltage rising ramp to prevent too much delay between two components startup. It is better to start from 0V with all circuits fully discharged with no residual voltages, see Power down sequence for more information. The voltage curve should be monotonic and strictly rising.

The rising time is conditioned by the total capacitance (in Farads) of the circuit (chip + decoupling + components) as well as the impedance of the power supply Z_SUPPLY or the current limit i_MAX.

If the inrush current is too high, the voltage may drop during rising, and not be strictly rising or the power supply can shut off if an over current protection is triggered. For more information see section Current limiting.

1.3.3. Over current protection

Most simple power supplies do not have any current management. In the case of short circuit or low impedance load, this can lead to destructive current for the power supply or the load. Furthermore, in some cases there are current limitations from the power source. To improve the quality and robustness of the application it is recommended to choose a power supply with a current protection feature.

Over current cut off

A simple solution is monitoring the current and cutting power supply off when it reaches the limit. It is a simple and efficient solution, however if threshold is too low, it can be triggered by current spike like inrush current.

Current limiting

Power supplies with current limiting feature, adjust voltage to never exceed maximum current. This protects against short circuits and can be used to limit inrush current. It has the advantage of not power off completely in case of transient spike of current. As illustrated on the figure below, the voltage drops when the current limit is reached, the powers supply switches in constant current mode.

Illustration of output current limiting with a sinusoidal load

Note: A current limiting can lead to ripple around the startup voltage. When VDD passes over power-on reset threshold, reset is released, and the STM32 starts to operates. If the current call is too high, the limiting current lowers the voltage, eventually enough to go back under power-down reset threshold that reset the MCU. This can be repeated multiple times until capacitors are eventually charged enough. The application resets multiple times before starting for good or may even never starts. As illustrated in the side figure VDD oscillate around Nreset threshold.

Startup issue: voltage ripple with current limit to low

1.3.4. Soft start

Soft start is another way to control inrush current. It consists of a controlled, slow voltage rising ramp.

Example components:

• L7983 is an SMPS controller which include a soft start feature, the output voltage rises in 2 ms: DS13354 - Rev 1, ch 5.4, p17.
• LD59150 is an LDO with a programmable soft start and a power good signal: DS12455 - Rev 7, ch 6.2, p8.

1.3.5. Over voltage protection (OVLO)

Overvoltage lockout (OVLO) feature cuts output power when voltage reaches an overvoltage threshold. This prevents damaging the load in case of unexpectedly high input voltage. STBP120 is a power supervisor IC that provides multiple features including OVLO.

1.3.6. Under voltage lockout (UVLO)

Under voltage lockout consist of cutting output power when input voltage passes below a threshold. This prevents powering the load with intermediate voltage. The ST1PS03 is a buck converter (SMPS) which includes under voltage lockout.

1.3.7. Power good signal

Power good signal can be provided either by the power supply itself or by a power monitor device, tells when voltage is high enough and stabilized. Is useful to keep reset an IC during supply start-up to play the role of internal Power supply supervisor. It is also used to enable another power supply to manage power one order for example.
For example, LDL40 and LD59150 are LDO with an integrated PG feature.
Here finds external power supervisor which implements some functionalities presented above: https://www.st.com/en/reset-and-supervisor-ics.html.

1.3.8. Power down sequence

V_DD falling scenarios.

The importance of power down phase is frequently underestimated. It recommended to always keep a low impedance tied on V_DD, even for power down phase. To properly discharge all capacitance, pull V_DD to 0V with a low impedance. There are different methods to implement proper power down.

Passive resistor

A resistor, RD, places between V_DD and GND discharge capacitors when power supply is off. Discharge time lasts about $3*\tau =3RC\ ;\ R=R_{D}$ and C is the sum of all decoupling/bulk capacitors. This is a low-cost solution, but it consumes power permanently: $P={{V_{DD}}^{2} \over R_{D}}$ . The lower the pull-down resistor, the quicker the discharge and higher is the consumption.

power rail discharge resistor

Power monitor + Mos

power rail discharge transistor

This solution uses a resistor in series with a transistor controlled by a inverted power good or enable signal. Two important elements to take care:

• Ensure that V_DD rail is not powered when closing discharge switch, either by disabling the regulator or be sure that no more power source is connected. Otherwise, this led to a huge current call.
• The discharge switch gate needs to be held above V_GS threshold until V_DD rail reaches 0V. This can be challenging if Vin drops quickly. Consider these parameters to ensure functional circuit:
  • Use a low V_GS N-Channel MOSFET transistor.
  • Adding capacitor in the power monitor supply domain can help to keep it powered longer.
  • Use a lower resistor to discharge V_DD rail quicker.
  • Set a high Vin threshold to give more time margin.

PS integrated discharge

The most efficient way to implement this feature is to use a fully integrated in power supply itself. This reduces overall complexity, conception time, number of components and used space on PCB.
Some power supplies, equipped with an enable feature, has an internal switch that ties the Vout line to ground when disabled.
For example, the STLQ020 is a LDO with an optional discharge feature through a 100Ω resistor when enable signal is low.
The ST1PS03 is a buck converter (SMPS) which includes output discharge feature.

Output discharge feature SMPS; ST2PS03: DS13206 - Rev 4

1.3.9. Components example

• ST1PS02 SMPS regulator; 400-mA buck regulator:
  • Adjustable output current limit
  • Power good signal
  • Constant current soft start
  • Output discharge
  • Under voltage protection
• ST1L08 LDO regulator; 800-mA high PSRR linear regulator:
  • Power good signal
  • Current limiter
  • Enable signal
  • Thermal protection
• STEF05 eFuse:
  • Soft start
  • Output voltage clamp
  • Current limiting

2. STM32

2.1. Context

STM32 microcontrollers are composed of different power domains. This has different purposes:

• Have different operating voltage.
• Have different power sources.
• Shut down some parts to reduce power consumption.
• Isolate from perturbations.

The main supply of STM32 is called V_DD. On simplest products and/or smallest packages, this is used to supply the entire device. Slightly more advanced products have other input power supplies dedicated to specific features like analog peripherals, GPIO, USB, SPI, LCD.

Some STM32 are internally divided into different power domains. They can be separated by power switches or regulators. Thanks to that some power domains can be completely unpowered when not used. For example, STM32H747/757 as explained in the [AN5215].

2.2. Specific supplies configurations

2.2.1. V_CORE/V_CAP

V_CORE power scheme STM32H7; AN4938 Rev 6

CPU, memory, and some peripherals are part of Core domain or V_CORE domain. This voltage rail is generally provided by an internal LDO. On some products, CPU voltage supply (V_CORE) is externally accessible through V_CAP pin, in this case there is different way to supply V_CORE power domain:

V_CORE supply configurations

Internal LDO

LDO Supply (1st configuration) V_CORE provided by the internal LDO supplied with V_DD. This requires decoupling capacitor on V_CAP for the stability of the internal LDO.

External regulator

Bypass (6th configuration) It is possible to externally supply V_CORE through V_CAP bypassing the internal LDO.

Internal SMPS

In some devices, an internal SMPS is available. It can be used to be more efficient.
Direct SMPS supply (2nd configuration) The internal SMPS can supply directly V_CORE to get better efficiency.
SMPS supplies LDO (3rd configuration) To reduce the ripple from SMPS, supply the Internal LDO by the SMPS. The SMPS output is about 100mV above V_CORE, and the LDO filters the ripple.

Note: Depending on configuration recommended decouppling caps have different values.
Note: Some STM32 with V_CAP available does not allow bypass of internal regulator. Always verify in product datasheet or reference manual that supply configuration is allowed.

2.2.2. V_DDA Vref

When V_DDA pins are available on the packager, the analog power domain is separated from the digital power domain to reduce the impact of digital switching noise. Analog components such as ADC, comparators, DAC are supplied by V_DDA.
For sensitive applications, V_DDA can be provided by a separate power supply like a low noise and high PSRR LDO. If not possible, the minimal recommendation is to connect V_DDA to V_DD with a ferrite bead in series.

Example ferrite reference design STM32H7x3; AN4938 Rev 6

The main sensitive point regarding noise and accuracy is Vref which is the voltage reference used by analog components. This means that ADC measurement accuracy and noise (SNR) directly dependent on Vref. Vref is generally accessible through Vref+ pin.

Vref can be provided in different ways.

• The simplest solution is to use V_DDA. The smallest packages have Vref+ directly bounded to V_DDA. Otherwise, it is possible to directly tie Vref+ and V_DDA together. In this case, V_DDA is more sensitive to noise and accuracy.
• Some products embed an internal bandgap reference Vrefbuf which can provide a steady voltage reference which doesn't depend on V_DDA precision and filter its noise. This adds a filtering step and is easy to implement as it is integrated inside the STM32. As trade of the bandgap reference consumes current. This configuration require a capacitor in Vref+ pin.
• Finally, it is possible to provide an external reference through Vref+ pin provided by a dedicated component.

vref buf extract from stm32U535 datasheet DS14217 rev4 p62

Decoupling: STM32 datasheets provide decoupling scheme depending on the wiring of Vref.

In conclusion, noise and accuracy of analog devices depends on Vref noise and accuracy. Not respecting wiring and decoupling recommendation could lead to perturbations on Vref so impact analog devices performances.

2.3. Power consumption factors

There are multiple factors that influence the STM32 consumption.

2.3.1. Voltage

Digital IC consumes more current when operating at higher voltage. Some STM32 has a range of operating voltages, this able to choose the voltage level to reduce consumption. The core voltage V_CORE selected by VOSx and peripherals such as V_DDIO or V_DDX voltage can be modulated depending on the product. Keep in mind that lowering voltage lowers the maximum operating frequency. Important note: A current spike is drawn when increasing voltage, current spike that must be handled by the power supply.

2.3.2. Frequency

STM32 consumption depends on the clock frequency, higher the clock speed is, higher the current. Lowering the CPU or peripheral clock frequency helps to reduce the current consumption.
Important note: A current spike is drawn when increasing frequency, current spike that must be handled by the power supply.

2.3.3. Peripherals

On STM32 peripherals are dynamically configurable, they can be deactivated when not used. Disactivating a peripheral, by removing its clock, disconnecting IOs pins and reconfiguring registers, reduces overall consumption.

2.3.4. CPU Modes / Low power Modes

STM32 has different operating modes (Run, Sleep, Stop, Standby, Low power Run, Low power Sleep, ...) that enable/disable peripherals, functionalities and change operating frequencies and voltage. These are used to reduce power consumption when some features are not used by the application.
See this article for more information: https://wiki.st.com/stm32mcu/wiki/Getting_started_with_PWR.
Note: Keep in mind that waking up MCU from sleep or stop modes take time and consume current. It is longer to wake up from deeper sleeping mode. Some parameters like clock frequency help to have a quicker wakeup at the price of a higher peak current.

2.3.5. Temperature

Physical properties of materials, especially resistivity, are affected by temperature. Digital IC consumes significantly more at high temperatures.

2.3.6. Conclusion

Example: current consumption/spikes at wake up stop2, change Vos and frequency STM32U545

Reducing voltage, frequency and deactivating unused peripherals reduces overall consumption. Keep in mind that increasing voltage, frequency or reactivating voltage regulators or peripherals often induces a current spike.

2.4. How to estimate consumption

2.4.1. STM32CubeMX Power Consumption Calculator (PCC)

To estimate power consumption, Stm32CUBEMX software integrates a tool called Power Consumption Calculator (PCC). This is an interesting complementary tool to the manual approach presented in this chapter. See STM32CubeMX User manual (UM1718) chapter 13 "Using the Power Consumption Calculator to optimize the embedded application consumption and more" to learn more.

2.4.2. Configuration consumption

Many parameters can be configured dynamically during application execution, this modifies consumption. The first step is estimating consumption of different configurations.
The first thing to look at is the system consumption. Datasheet usually system consumption with all peripherals disabled for different mode, clock, and memory configuration. The consumption includes Clock source, program memory and CPU. Note that datasheets usually give typical and maximum values at different temperatures.'
Then look at each peripheral consumption depending on their configurations.
The total consumption is the sum of all component's consumption. As generally CPU value is given for the whole MCU except peripherals, add to this each activated peripherals consumption.
Note: Current is measured at Vdd level, as shown in current consumption measurement table in STM32 datasheets. For STM32 with integrated SMPS, datasheets provide different consumption values with internal LDO and internal SMPS.
Note: Current measurements are provided for specific conditions specified in datasheet.

Example: STM32F405RG in run mode, executing code from Flash memory, running at 90MHz with all peripherals disabled consume 20 mA in typical conditions at 25°C:	Example: STM32L073V8 in run mode, Range2 (VCORE = 1,5V), FHCL = 16MHz, FAPB2= 8MHz, the USART1 consume 11.5 µA/MHz so: 92µA in typical conditions:
Extract datasheet STM32F405RG; DS8626 Rev 9; table 20	Extract datasheet STM32L073V8; DS10685 Rev 7; table 40

2.4.3. Average current

To calculate the average current, sum the consumption of CPU for each configuration pondered with time ratio spend in it add to that consumption of each peripheral at given configuration pondered with use time ratio. The average current gives a long theme consumption, it relevant to estimate energy consumption and size a finite energy source like a battery.

$I_{avg}=\Sigma [(CPU+Clock+Memory)*usage\ ratio]+\Sigma [Peripheral\ Consumption*usage\ ratio]$

2.4.4. Maximum continuous current

Take the configuration that consumes the most in application conditions. This value must be lower than the maximum continuous current characteristic of the power supply.

2.4.5. Peak current

Inrush

One of the main sources of peak current is inrush during power up. Supply voltage rise charge capacitors of the circuit and startup of ICs draws current. This represents a significative amount of energy.
The inrush current might be much higher than other currents spikes in operating conditions. To reduce the size of the power supply, it is possible to control inrush, either using a current limiting feature in the power supply or soft start, see Soft start section for more information.
Three elements are related, total capacitance, rising time and peak current. Always remember that tuning one affects the others.
Note: This topic is related to rising time, see Power on sequence section. The faster the voltage rises, the higher the current is. $i_{rush}=C_{eq}*{dV_{DD} \over dt}$; ${dV_{DD} \over dt}$ is the rising rate, C_EQ equivalent capacitance of the system, sum of all decoupling/bulk capacitor, capacitance of the different components/chip.

Mode transition

Transitioning between different run/operating modes, low power modes, clock frequency, voltage ranges induce transient current that might be significative for sensitive applications.
Wakeup consumption is given in datasheet in Ampere seconds (Coulombs), it corresponds to the total charge consume to wake up, here is the example of STM32U535:

Wake up from	Stop1	Stop3	Standby
nAs(nano Coulombs)	70	610	3200
STM32U353 wakeup Consumption from different modes

2.5. STM32 supply pins reference decoupling scheme

It is recommended to put small capacitors for each power supply pin, and some bigger for the whole circuit. In any case refer to the "Power supply scheme" figure int device Datasheet. When there is multiple power domain decoupling is needed for each one. When V_CAP is available, decoupling capacitors need to be attached as close as possible to V_CAP pins.
Here is the example of the STM32 L0: 100nF for each supply pins and an additional 10µF for each power domain.

Decoupling scheme example; STM32 L0

PCB recommendations

The PCB layout plays an important role in the quality of decoupling, refer to the Getting started application note, dedicated to the STM32 model, to get precises guidelines.
Generally speaking, it's important to have low impedance power plans.

2.6. Power supply supervisor

To ensure that that the MCU does not run under the minimum operating voltage, STM32 devices have integrated voltage monitoring circuitry.

2.6.1. System reset

A system reset sets all the registers to their default values except the reset flags in the clock controller RCC_RSR register and the registers in the backup domain. A system reset is generated when one of the following events occurs:

• A low level on the NRST pin (external reset)
• Window watchdog end of count condition (WWDG reset)
• Independent watchdog end of count condition (IWDG reset)
• A software reset (Software reset)
• A low-power management reset.

2.6.2. Power-on reset (POR)/power-down reset (PDR)

STM32 power supply supervisors

The STM32 remains in reset mode while V_DD is below a specified threshold, VPOR/PDR, generally around 1.7V-1.8V. For more details concerning t_RSTTEMPO and VPOR/VPDR threshold value refer to the "electrical characteristics" and "reset and power control block characteristics table" in the mcu datasheet.
On some devices the PDR_ON pin is available. In this case the power supply supervisor is enabled by holding PDR_ON high and can be disabled by pulling down PDR_ON. Otherwise, if not available the power supply supervisor is always enabled.
If power supply supervisor is disabled, an external power supply supervisor must monitor V_DD and control the NRST pin. The device must be maintained in reset mode as long as V_DD is below the minimum operating voltage specified in the datasheet.
The supply ranges which never go below VPOR/PDR are managed more effectively using the internal circuitry (no additional components are needed, thanks to the fully embedded reset controller). When the embedded power supply supervisor is off, the following integrated features are no longer supported:

• the integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• the brown out reset (BOR) circuitry must be disabled.
• the embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no longer available and VBAT pin must be connected to V_DD.

2.6.3. Brownout reset (BOR)

The BOR keeps the system under reset until the V_DD supply voltage reaches the selected VBOR threshold.
BOR is enabled through the option bytes, as well as VBOR threshold. Different BOR levels are available depending on the device. It is used to set a higher threshold than VPOR and can be modified dynamically, see the device reference manual or datasheet for more information.

2.6.4. Programmable voltage detector (PVD)

The PVD is an additional voltage monitoring system. It sets a flag that tells if V_DD is above or below the selected threshold. PVD is activated and the threshold VPVD selected through registers, see the device reference manual or datasheet for more information.
It can be connected to the EXTI to trigger interruption when V_DD drops below the selected threshold or rise above the threshold. As an example, the service routine could perform emergency shutdown tasks such as saving data in backup domain.
Analog voltage detector (AVD) The AVD can be used to monitor V_DDA power supply like the PVD.

2.7. Multiple power supplies rules

2.7.1. Voltage differences

Different power domains have constraints about voltage differences. The datasheet specifies when one voltage needs to be higher than a second one, or the voltage difference might not exceed a certain value. For example, V_DDA vs V_DDX for STM32L0:

extract from STM32L073 datasheet; DS10685 Rev 7; table 23

Here is the case of STM32U5 product: V_DDA V_DDUSB and V_DDIO2 vs V_DD:

V_DDX vs V_DD STM32U535; DS14217 Rev 4; fig 4

2.7.2. Circuit examples

A simple way to ensure that a supply voltage V_DDX doesn't rise before V_DD, is to wire power good signal from V_DD regulator to enable signal of V_DDX regulator as shown in Figure below Sequencing power rails, chained regulators.

Sequencing power rails, chained regulators

Also be sure that V_DDX regulators have proper discharge feature to prevent any V_DDX staying above V_DD during power down phase.
In Figure below delayed Vddusb5 graph, an example of system above applied on Vdd5USB. Se during power down phase Vdd5USB must discharge fast enough to reach 1V before V_DD.

delayed Vddusb5 graph

3. Glossary

3.1. General

• AC: Alternative Current
• ADC: Analog to Digital Convertor
• CPU: Central Processing Unit
• DAC: Digital to Analog Convertor
• DC: Direct Current
• ESL: Equivalent Serial Inductance
• ESR: Equivalent Serial Resistor
• GPIO: General Purpose Inputs Outputs
• IC: Integrated Circuit, general term for silicon chips.
• LDO: Low DropOut linear regulator
• MCU: MicroController Unit
• OVLO: Over voltage protection
• PCB: Printed Circuit Board
• PS: Power Supply
• PSRR: Power-Supply Rejection Ratio
• RFID: Radio Frequency IDentification
• SMPS: Switching Mode Power Supplies
• SNR: Signal Noise Ratio, This corresponds to the noise level compared with signal level. This is commonly used to characterize signal treatments.
• SPI: Serial Peripheral Interface, serial communications interface
• STM32: STMicroelectronics microcontrollers 32 bits family
• USB: Universal Serial Bus, serial communications interface
• UVLO: Under voltage lockout

3.2. STM32 specific

• AVD: Analog Voltage Detector
• BOR: BrownOut Reset
• EXTI: EXTernal Interrupt,
• NRST: Not Reset signal, reset IC if low
• PDR: Power Down Reset
• PG: Power Good signal
• POR: Power On Reset
• PVD: Programmable Voltage Detector
• V_CORE: supply voltage for CPU
• V_DDA: main supply voltage of circuit
• V_DDA: supply voltage for analog peripherals
• V_DDIO: supply voltage for GPIO
• V_DDX: supply voltage for peripheral X