STM internal peripheral

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1. Article purpose[edit source]

The purpose of this article is to:

briefly introduce the STM peripheral and its main features
indicate the level of security supported by this hardware block
explain how each instance is allocated to each of the three runtime contexts and linked to the corresponding software components
explain, when necessary, how to configure the STM peripheral.

2. Peripheral overview[edit source]

The STM peripheral is used to log STM traces into the embedded trace FIFO (ETF). This trace can include hardware events (the list is given in the STM32MP15 reference manuals) or direct 'printf like' log from the Cortex^®-A7. Once in the ETF buffer, the trace can be dumped directly from the Cortex^®-A7 or to the trace port interface unit (TPIU), connected to an external probe able to decode it.

2.1. Features[edit source]

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.

2.2. Security support[edit source]

The STM is a non secure peripheral.

2.3. Boot time[edit source]

The STM can be used to debug the boot sequence using external probe.

2.4. Runtime[edit source]

2.4.1. Overview[edit source]

The STM can be used to debug the run time application using external probe.

2.4.2. Software frameworks[edit source]

There is no software dedicated to the STM internal peripheral delivered with the STM32MPU ecosystem. Nevertheless, the STM trace can be captured using an external probe.

2.4.3. Peripheral configuration[edit source]

Configuration of the STM is done via JTAG scripts. Those scripts must be built by the user using the STM32MP15 reference manuals .

2.4.4. Peripheral assignment[edit source]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Trace & Debug	STM	STM				No assignment possible