SPI internal peripheral

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the SPI peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the SPI peripheral and for some of them the I2S features.

2 Peripheral overview[edit]

The SPI peripheral can be used to communicate with an external devices using the SPI (Serial Peripheral Interface).
A subset of the SPI instances supports the I2S audio protocol. These SPI/I2S peripherals can alternatively be used in audio applications, when they are configured as an I2S interface. Refer to peripheral assignment chapter to check I2S feature support for each SPI instance.

2.1 Features[edit]

2.1.1 SPI main features[edit]

  • Full-duplex, half-duplex and simplex synchronous modes.
  • Slave and master modes.

2.1.2 I2S main features[edit]

Only available for SPI supporting I2S mode.

  • Full-duplex or simplex modes.
  • Slave and master modes.
  • Four audio protocols supported.

2.1.3 Specific features[edit]

Some of the SPI peripheral characteristics depend on I2S support, as summarized in following table:

SPI modes/features I2S supported I2S not supported
Rx & TxFIFO size (N) [x 8-bit] 16 8
Maximum configurable data size [bits] 32 16

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

SPI6 is a secure peripheral (under ETZPC control).
The other SPI instances are non-secure peripherals.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The SPI is not used at boot time.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The SPI6 can be allocated to:

  • the Arm® Cortex®-A7 secure core to be controlled in OP-TEE by the SPI OP-TEE driver

All the SPI instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by:
  • the SPI framework for SPI configured in SPI mode
  • the ALSA framework for SPI configured in I2S mode


Chapter Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment

Low speed interface SPI OP-TEE SPI driver Linux SPI framework STM32Cube SPI driver SPI configured in SPI mode
The OP-TEE SPI driver is not yet available
Audio SPI Linux ALSA framework STM32Cube SPI driver SPI configured in I2S mode
Only for SPI supporting I2S feature

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be done via STM32CubeMX tool for all internal peripheral, then it can manually be completed (especially for external peripherals) according to the information given in the corresponding software framework article.

When the Arm® Cortex®-A7 core operates in non-secure access mode, the SPI is controlled by the Linux kernel framework.

  • SPI mode:

Refer to SPI framework to check how to drive SPI through Linux kernel.

  • I2S mode:

Refer to I2S Linux driver to drive the SPI through Linux kernel ALSA framework. Refer to Soundcard configuration to configure it through the Linux kernel device tree[1].

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7

Low speed interface
SPI SPI2S1 Assignment (single choice)
SPI2S2 Assignment (single choice)
SPI2S3 Assignment (single choice)
SPI4 Assignment (single choice)
SPI5 Assignment (single choice)
SPI6 Assignment (single choice)

4 References[edit]