1. Article purpose[edit source]
The purpose of this article is to
- briefly introduce the OTG peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how it can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when needed, how to configure the OTG peripheral.
2. Peripheral overview[edit source]
The OTG peripheral is used to interconnect other systems with STM32 MPU devices, using USB standard.
2.1. Features[edit source]
The OTG peripheral is a USB Dual-Role Device (DRD) controller that supports both device and host functions.
In Host mode, it supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).
In Peripheral mode, high-speed and full-speed are supported, not low-speed.
The OTG peripheral embeds a full-speed PHY and supports a UTMI interface connected to internal HS PHY.
The OTG peripheral is fully compliant with
- On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification[1], Revision 2.0, May 8, 2009
- Universal Serial Bus Revision 2.0 Specification[2], Revision 2.0, April 27, 2000
- USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification[3], July 16, 2007
- USB 2.0 Transceiver Macrocell Interface (UTMI) Specification[4], Version 1.05, March 29, 2001
- UTMI+ Specification[5], Revision 1.0, February 25, 2004
Refer to STM32MP15 reference manuals for the complete hardware feature list, and to the software components (introduced below) to know which features are supported.
2.2. Security support[edit source]
The OTG peripheral is a non-secure peripheral.
3. Peripheral usage and associated software[edit source]
3.1. Boot time[edit source]
The OTG peripheral is used by ROM code, FSBL and SSBL in device mode (DFU) to support serial boot for flash programming with STM32CubeProgrammer.
The SSBL can use it in host mode (mass storage), for instance to boot on a kernel stored on a USB key, or after a kernel panic to perform the crash dump saving to the USB key.
3.2. Runtime[edit source]
3.2.1. Overview[edit source]
The OTG peripheral can be allocated to the Arm® Cortex®-A7 non-secure core to be used under Linux® with USB framework.
3.2.2. Software frameworks[edit source]
| Domain | Peripheral | Software frameworks | Comment | ||
|---|---|---|---|---|---|
| Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| High speed interface | OTG (USB OTG) | Linux USB framework | |||
3.2.3. Peripheral configuration[edit source]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.
For Linux kernel configuration, please refer to OTG device tree configuration.
For U-boot configuration, please refer to Configure USB OTG node in U-Boot.
3.2.4. Peripheral assignment[edit source]
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| High speed interface | OTG (USB OTG) | OTG (USB OTG) | ☐ | |||
4. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.