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This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.<br> | This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.<br> | ||
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found. | Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found. | ||
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Several '''runtime contexts''' exist on STM32MP15 device<ref name="STM32MPU multiple cores">[[Getting started with STM32 MPU devices#Multiple-core architecture concepts]]</ref>, corresponding to the different '''Arm cores and associated security modes''': | Several '''runtime contexts''' exist on STM32MP15 device<ref name="STM32MPU multiple cores">[[Getting started with STM32 MPU devices#Multiple-core architecture concepts]]</ref>, corresponding to the different '''Arm cores and associated security modes''': | ||
* <span style="color:#FFFFFF; background: | * <span style="color:#FFFFFF; background:{{STPink}};"> Arm dual core Cortex-A7 secure </span> (Trustzone), running a Secure Monitor or Secure OS like [[OP-TEE overview|OP-TEE]] | ||
* <span style="color:#FFFFFF; background: | * <span style="color:#FFFFFF; background:{{STDarkBlue}};"> Arm dual core Cortex-A7 non secure </span>, running [[STM32MP15 Linux kernel overview|Linux]] | ||
* <span style="color:#FFFFFF; background: | * <span style="color:#FFFFFF; background:{{STLightBlue}};"> Arm Cortex-M4 </span> (non-secure), running [[STM32CubeMP1 architecture|STM32Cube]] | ||
<br /> | <br /> | ||
Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br /> | Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br /> | ||
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{{ | {{ | ||
ImageMap| | ImageMap| | ||
Image:STM32MP1IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP1 internal peripherals overview | Image:STM32MP1IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP1 internal peripherals overview | ||
rect 18 113 103 141[[STGEN internal peripheral | STGEN]] | rect 18 113 103 141[[STGEN internal peripheral | STGEN]] | ||
rect 18 146 103 175[[SYSCFG internal peripheral | SYSCFG]] | rect 18 146 103 175[[SYSCFG internal peripheral | SYSCFG]] | ||
| Line 58: | Line 50: | ||
rect 400 306 484 333[[GPIO internal peripheral | GPIO]] | rect 400 306 484 333[[GPIO internal peripheral | GPIO]] | ||
rect 492 306 577 333[[GPIO internal peripheral | GPIO]] | rect 492 306 577 333[[GPIO internal peripheral | GPIO]] | ||
rect | rect 354 41 438 68 [[IPCC internal peripheral | IPCC]] | ||
rect 447 41 531 68 [[HSEM internal peripheral | HSEM]] | |||
rect 13 418 97 444 [[RCC internal peripheral | RCC]] | rect 13 418 97 444 [[RCC internal peripheral | RCC]] | ||
rect 13 450 97 478 [[PWR internal peripheral | PWR]] | rect 13 450 97 478 [[PWR internal peripheral | PWR]] | ||
| Line 69: | Line 62: | ||
rect 215 450 299 478 [[FMC internal peripheral | FMC]] | rect 215 450 299 478 [[FMC internal peripheral | FMC]] | ||
rect 214 484 299 512 [[SDMMC internal peripheral | SDMMC]] | rect 214 484 299 512 [[SDMMC internal peripheral | SDMMC]] | ||
rect | rect 412 485 497 512 [[FDCAN internal peripheral | FDCAN]] | ||
rect | rect 501 485 585 512 [[ETH internal peripheral | ETH]] | ||
rect | rect 316 384 401 412 [[SDMMC internal peripheral | SDMMC]] | ||
rect | rect 316 418 401 445 [[USBH internal peripheral | USBH]] | ||
rect | rect 316 451 401 479 [[OTG internal peripheral | OTG]] | ||
rect 316 484 401 511 [[USBPHYC internal peripheral | USBPHYC]] | |||
rect 413 369 497 396 [[USART internal peripheral | USART]] | rect 413 369 497 396 [[USART internal peripheral | USART]] | ||
rect 413 | rect 413 402 497 430[[USART internal peripheral | USART]] | ||
rect 502 369 586 396 [[USART internal peripheral | USART]] | rect 502 369 586 396 [[USART internal peripheral | USART]] | ||
rect 413 | rect 413 437 497 463 [[I2C internal peripheral | I2C]] | ||
rect 502 | rect 502 402 586 430 [[I2C internal peripheral | I2C]] | ||
rect 502 | rect 502 437 586 463 [[I2C internal peripheral | I2C]] | ||
rect 591 369 674 396 [[SPI internal peripheral | SPI]] | rect 591 369 674 396 [[SPI internal peripheral | SPI]] | ||
rect 591 | rect 591 402 674 430 [[SPI internal peripheral | SPI]] | ||
rect 709 113 792 140 [[RNG internal peripheral | RNG]] | rect 709 113 792 140 [[RNG internal peripheral | RNG]] | ||
rect 800 113 883 140 [[HASH internal peripheral | HASH]] | rect 800 113 883 140 [[HASH internal peripheral | HASH]] | ||
| Line 106: | Line 100: | ||
rect 800 485 883 512 [[SAI internal peripheral | SAI]] | rect 800 485 883 512 [[SAI internal peripheral | SAI]] | ||
}} | }} | ||
==Internal peripherals assignment== | ==Internal peripherals assignment== | ||
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==References== | ==References== | ||
<references/> | <references/> | ||
<noinclude> | |||
{{PublicationRequestId | 9171 | 2018-10-17 | AlainF}} | |||
[[Category:Peripherals overview]] | |||
[[Category:STM32MP15]] | |||
</noinclude> | |||
Latest revision as of 15:48, 22 January 2020
This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.
1. Internal peripherals overview[edit source]
The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.
Several runtime contexts exist on STM32MP15 device[1], corresponding to the different Arm cores and associated security modes:
- Arm dual core Cortex-A7 secure (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
- Arm dual core Cortex-A7 non secure , running Linux
- Arm Cortex-M4 (non-secure), running STM32Cube
Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:
Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.
2. Internal peripherals assignment[edit source]
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Analog | ADC | ADC | ☐ | ☐ | Assignment (single choice) | |
| Analog | DAC | DAC | ☐ | ☐ | Assignment (single choice) | |
| Analog | DFSDM | DFSDM | ☐ | ☐ | Assignment (single choice) | |
| Analog | VREFBUF | VREFBUF | ☐ | Assignment (single choice) | ||
| Audio | SAI | SAI1 | ☐ | ☐ | Assignment (single choice) | |
| SAI2 | ☐ | ☐ | Assignment (single choice) | |||
| SAI3 | ☐ | ☐ | Assignment (single choice) | |||
| SAI4 | ☐ | ☐ | Assignment (single choice) | |||
| Audio | SPDIFRX | SPDIFRX | ☐ | ☐ | Assignment (single choice) | |
| Coprocessor | IPCC | IPCC | ☑ | ☑ | Shared (none or both) | |
| Coprocessor | HSEM | HSEM | ✓ | ✓ | ✓ | |
| Core | RTC | RTC | ✓ | ✓ | RTC is mandatory to resynchronize STGEN after exiting low-power modes. | |
| Core | STGEN | STGEN | ✓ | ✓ | ||
| Core | SYSCFG | SYSCFG | ✓ | ✓ | ||
| Core/DMA | DMA | DMA1 | ☐ | ☐ | Assignment (single choice) | |
| DMA2 | ☐ | ☐ | Assignment (single choice) | |||
| Core/DMA | DMAMUX | DMAMUX | ☐ | ☐ | Shareable (multiple choices supported) | |
| Core/DMA | MDMA | MDMA | ☐ | ☐ | Shareable (multiple choices supported) | |
| Core/Interrupts | EXTI | EXTI | ☐ | ☐ | Shareable (multiple choices supported) | |
| Core/Interrupts | GIC | GIC | ✓ | ✓ | ||
| Core/Interrupts | NVIC | NVIC | ✓ | |||
| Core/IOs | GPIO | GPIOA (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |
| GPIOB (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOC (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOD (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOE (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOF (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOG (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOH (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOI (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOJ (16 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOK (8 pins) | ☐ | ☐ | Shareable (with pin granularity) | |||
| GPIOZ (8 pins) | ☐ | ☐ | ☐ | Shareable (with pin granularity) | ||
| Core/RAM | BKPSRAM | BKPSRAM | ☐ | ☐ | Assignment (single choice) | |
| Core/RAM | DDR via DDRCTRL | DDR | ✓ | ✓ | ||
| Core/RAM | MCU SRAM | SRAM1 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) |
| SRAM2 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
| SRAM3 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
| SRAM4 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
| Core/RAM | RETRAM | RETRAM | ☐ | ☐ | ☐ | Assignment (single choice) |
| Core/RAM | SYSRAM | SYSRAM | ☐ | ☐ | Shareable (multiple choices supported) | |
| Core/Timers | LPTIM | LPTIM1 | ☐ | ☐ | Assignment (single choice) | |
| LPTIM2 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM3 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM4 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM5 | ☐ | ☐ | Assignment (single choice) | |||
| Core/Timers | TIM | TIM1 (APB2 group) | ☐ | ☐ | Assignment (single choice) | |
| TIM2 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM3 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM4 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM5 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM6 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM7 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM8 (APB2 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM12 (APB1 group) | ☐ | ☐ | ☐ | Assignment (single choice) | ||
| TIM13 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM14 (APB1 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM15 (APB2 group) | ☐ | ☐ | ☐ | Assignment (single choice) | ||
| TIM16 (APB2 group) | ☐ | ☐ | Assignment (single choice) | |||
| TIM17 (APB2 group) | ☐ | ☐ | Assignment (single choice) | |||
| Core/Watchdog | IWDG | IWDG1 | ☐ | |||
| IWDG2 | ☐ | ☐ | Shared (none or both):
| |||
| Core/Watchdog | WWDG | WWDG | ☐ | |||
| High speed interface | OTG (USB OTG) | OTG (USB OTG) | ☐ | |||
| High speed interface | USBH (USB Host) | USBH (USB Host) | ☐ | |||
| High speed interface | USBPHYC (USB HS PHY controller) | USBPHYC (USB HS PHY controller) | ☐ | |||
| Low speed interface | I2C | I2C1 | ☐ | ☐ | Assignment (single choice) | |
| I2C2 | ☐ | ☐ | Assignment (single choice) | |||
| I2C3 | ☐ | ☐ | Assignment (single choice) | |||
| I2C4 | ☐ | ☐ | Assignment (single choice). Used for PMIC control on ST boards. | |||
| I2C5 | ☐ | ☐ | Assignment (single choice) | |||
| I2C6 | ☐ | ☐ | Assignment (single choice) | |||
| Low speed interface or audio |
SPI | SPI2S1 | ☐ | ☐ | Assignment (single choice) | |
| SPI2S2 | ☐ | ☐ | Assignment (single choice) | |||
| SPI2S3 | ☐ | ☐ | Assignment (single choice) | |||
| SPI4 | ☐ | ☐ | Assignment (single choice) | |||
| SPI5 | ☐ | ☐ | Assignment (single choice) | |||
| SPI6 | ☐ | ☐ | Assignment (single choice) | |||
| Low speed interface | USART | USART1 | ☐ | ☐ | Assignment (single choice) | |
| USART2 | ☐ | ☐ | Assignment (single choice) | |||
| USART3 | ☐ | ☐ | Assignment (single choice) | |||
| UART4 | ☐ | ☐ | Assignment (single choice). Used for Linux® serial console on ST boards. | |||
| UART5 | ☐ | ☐ | Assignment (single choice) | |||
| USART6 | ☐ | ☐ | Assignment (single choice) | |||
| UART7 | ☐ | ☐ | Assignment (single choice) | |||
| UART8 | ☐ | ☐ | Assignment (single choice) | |||
| Mass storage | FMC | FMC | ☐ | |||
| Mass storage | QUADSPI | QUADSPI | ☐ | ☐ | Assignment (single choice) | |
| Mass storage | SDMMC | SDMMC1 | ☐ | |||
| SDMMC2 | ☐ | |||||
| SDMMC3 | ☐ | ☐ | Assignment (single choice) | |||
| Networking | ETH | ETH | ☐ | Assignment (single choice) | ||
| Networking | FDCAN | FDCAN1 | ☐ | ☐ | Assignment (single choice) | |
| FDCAN2 | ☐ | ☐ | Assignment (single choice) | |||
| Power & Thermal | DTS | DTS | ☐ | |||
| Power & Thermal | PWR | PWR | ✓ | ✓ | ✓ | |
| Power & Thermal | RCC | RCC | ✓ | ✓ | ✓ | |
| Security | BSEC | BSEC | ✓ | ✓ | ||
| Security | CRC | CRC1 | ☐ | |||
| CRC2 | ☐ | |||||
| Security | CRYP | CRYP1 | ☐ | ☐ | Assignment (single choice) | |
| CRYP2 | ☐ | |||||
| Security | ETZPC | ETZPC | ✓ | ✓ | ✓ | |
| Security | HASH | HASH1 | ☐ | ☐ | Assignment (single choice) | |
| HASH2 | ☐ | |||||
| Security | RNG | RNG1 | ☐ | ☐ | Assignment (single choice) | |
| RNG2 | ☐ | |||||
| Security | TZC | TZC | ✓ | |||
| Security | TAMP | TAMP | ✓ | ✓ | ||
| Trace & Debug | DBGMCU | DBGMCU | No assignment | |||
| Trace & Debug | HDP | HDP | ☐ | |||
| Trace & Debug | STM | STM | No assignment possible | |||
| Visual | CEC | CEC | ☐ | ☐ | Assignment (single choice) | |
| Visual | DCMI | DCMI | ☐ | ☐ | Assignment (single choice) | |
| Visual | DSI | DSI | ☐ | |||
| Visual | GPU | GPU | ☐ | |||
| Visual | LTDC | LTDC | ☐ | |||
3. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 