Difference between revisions of "Ethernet device tree configuration"

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1 Article purpose[edit]

This article explains how to configure the Ethernet when it is assigned to the Linux® OS. In that case, it is controlled by the Ethernet framework

The configuration is performed using the device tree mechanism that provides a hardware description of the Ethernet peripheral, used by the STM32 DWMAC driver

2 DT bindings documentation[edit]

The Ethernet is a multifunction device.

Each function is represented by a separate binding document:

  • "Generic" Ethernet device tree bindings [1]
  • specific STM32 ETH device tree bindings[2]

3 DT configuration[edit]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.

3.1 DT configuration (STM32 level)[edit]

Ethernet peripheral nodes are located in stm32mp157cstm32mp151.dtsi [3] file with a disabled status and some required properties such as:

  • Physical base address and size of the device register map
  • STMMAC interrupts
  • stmmaceth clock and Rx, Tx clocks

This is a set of properties that may not vary for a given STM32MP device, such as: register addresses, interrupts, clocks, ...

ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_NONE>;
	interrupt-names = "macirq";
	clock-names = "stmmaceth",
		      "mac-clk-tx",
		      "mac-clk-rx",
		      "ethstp",
		      "syscfg-clk";
	clocks = <&rcc ETHMAC>,
		 <&rcc ETHTX>,
		 <&rcc ETHRX>,
		 <&rcc ETHSTP>,
		 <&rcc SYSCFG>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	power-domains = <&pd_core>;
	status = "disabled";
};

The required and optional properties are fully described in the bindings files.

Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2 Ethernet DT configuration (board level)[edit]

The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ("ethernet") should be updated to:

  • Enable the Ethernet block by setting status = "okay".
  • Configure the pins in use via pinctrl, through pinctrl-0 (default pins), pinctrl-1 (sleep pins) and pinctrl-names.
  • Configure Ethernet interface used phy-mode = "rgmii"., (rmii, mii, gmii).
  • Configure Ethernet max speed max-speed = <1000>"..
&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

3.3 DT configuration examples[edit]

The example below shows how to configure and enable an Ethernet instance at board level:

&ethernet0 {
   status = "okay";                             /* enable ethernet0 */ 
   pinctrl-0 = <&ethernet0_rmii_pins_a>;        /* configure pinctrl modes for ethernet0 */
   pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;  /* configure ethernet0_rmii_pins_sleep_a as sleep pinctrl configuration for ethernet0 */
   pinctrl-names = "default", "sleep";
   phy-mode = "rmii";                           /* configure ethernet phy mode for ethernet0 */
   max-speed = <100>;                           /* configure ethernet max speed for ethernet0 */
   phy-handle = <&phy0>;
   
   mdio0 {
       #address-cells = <1>;
       #size-cells = <0>;
       compatible = "snps,dwmac-mdio";
       phy0: ethernet-phy@1 {
           reg = <1>;                           /* configure ethernet phy @ for ethernet0 */
       };
   };
};

How to configure Ethernet for :

3.3.1 RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal)[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

3.3.2 RMII with 25MHz on ETH_CLK (no PHY Crystal), REF_CLK from PHY (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock)[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "eth-ck",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,
                <&rcc ETHCK_K>,                
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi [4] to add ETHCK pin in ethernet0_rmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA devicetree to generate 25Mhz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 1 49 23 11 11 PQR(1,1,1) >;
 };

3.3.3 RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock)[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "eth-ck",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,
                <&rcc ETHCK_K>,                
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,eth_ref_clk_sel;               /* In case of U-Boot */ 
      or
       st,eth-ref-clk-sel;               /* In case of Linux Kernel */ 
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rmii_pins_a>;
       pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rmii";
       max-speed = <100>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA to generate 50Mhz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 508.0 MHz => P = 50, Q = 60, R = 60 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
    cfg = < 1 49 11 9 9 PQR(1,1,1) >;
  };

3.3.4 RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal)[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,             
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
   };

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
           };
   };

3.3.5 RGMII with 25MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock)[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "eth-ck",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,
                <&rcc ETHCK_K>,                
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rgmii_pins_* node:
For example:

 <STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */

+ Need also to update TFA to generate 25Mhz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
   pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 1 49 23 11 11 PQR(1,1,1) >;
 };

3.3.6 RGMII with Crystal on PHY, no 125Mhz from PHY[edit]

   ethernet0: ethernet@5800a000 {
       compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
       reg = <0x5800a000 0x2000>;
       reg-names = "stmmaceth";
       interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                             <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                             <&exti 70 1>;
       interrupt-names = "macirq",
                         "eth_wake_irq",
                         "stm32_pwr_wakeup";
       clock-names = "stmmaceth",
                     "eth-ck",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp";
       clocks = <&rcc ETHMAC>,
                <&rcc ETHCK_K>,                
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>;
       st,syscon = <&syscfg 0x4>;
       snps,mixed-burst;
       snps,pbl = <2>;
       snps,en-tx-lpi-clockgating;
       st,eth_clk_sel;               /* In case of U-Boot */ 
      or
       st,eth-clk-sel;               /* In case of Linux Kernel */ 
       snps,axi-config = <&stmmac_axi_config_0>;
       snps,tso;
       power-domains = <&pd_core>;
       status = "disabled";
};

   &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                       reg = <0>;
               };
       };
   };

+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:

+ Need also to update TFA to generate 125Mhz clock (from PLL4P or PLL3Q):
for example if PLL4P in ed1 board: update fdts/stm32mp15xx-edx.dtsi

st,pkcs = <
 CLK_CKPER_HSE
 CLK_FMC_ACLK
 CLK_QSPI_ACLK
 - CLK_ETH_DISABLED
 + CLK_ETH_PLL4P
...
 /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
 pll4: st,pll@3 {
     compatible = "st,stm32mp1-pll";
     reg = <3>;
     cfg = < 3 124 5 11 11 PQR(1,1,1) >;
 };

3.4 DT configuration to reset Phy with GPIO[edit]

The example below shows how to configure GPIO to reset the Ethernet PHY.
This chapter is applicable for custom board where the Ethernet PHY reset signal is connected to a GPIO.
IMPORTANT, for STMicroelectronics boards it is not possible to use this configuration because there is no dedicated GPIO to reset PHY.

For kernel update see "reset-gpios" in Documentation/devicetree/bindings/net/ethernet-phy.yaml[5]

 &ethernet0 {
      status = "okay";
      pinctrl-0 = <&ethernet0_rgmii_pins_a>;
      pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
      pinctrl-names = "default", "sleep";
      phy-mode = "rgmii";
      max-speed = <1000>;
      phy-handle = <&phy0>;
      mdio0 {
              #address-cells = <1>;
              #size-cells = <0>;
              compatible = "snps,dwmac-mdio";
              phy0: ethernet-phy@0 {
                       reg = <0>;
                       reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
                       reset-assert-us = <1000>;
                       reset-deassert-us = <2000>;
              };
      };
 };

For U-Boot same syntax of kernel, except that "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so you can change these value in function eqos_start_resets_stm32 of file dwc_eth_qos.c[6]

4 How to configure Ethernet using CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5 References[edit]


<noinclude>

{{ArticleBasedOnModel | [[Peripheral or framework device tree configuration model]]}}
{{ArticleMainWriter | ChristopheR}}
{{ArticleApprovedVersion| ChristopheR | AlexandreT (Not Done), GeraldB (Not Done), ErwanL (Not Done), LoicP (KO W846)| No previous approved version | BrunoB - 02Jan'19 - 10170 | 14Jan'19}}

[[Category:Device tree configuration]]
[[Category:Ethernet]]</noinclude>

== Article purpose ==
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the [[Ethernet overview|Ethernet framework]]

The configuration is performed using the [[Device tree|device tree]] mechanism that provides a hardware description of the Ethernet peripheral, used by the STM32 DWMAC driver

== DT bindings documentation ==
The ''Ethernet'' is a multifunction device.

Each function is represented by a separate binding document:
* "Generic" Ethernet device tree bindings <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/stmmac.txt}}</ref>

* specific STM32 ETH device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/net/stm32-dwmac.txt}}</ref>


== DT configuration ==
This hardware description is a combination of the '''STM32 microprocessor''' device tree files (''.dtsi'' extension) and '''board''' device tree files (''.dts'' extension). See the [[Device tree]] for an explanation of the device tree file split. 

=== DT configuration (STM32 level) ===

Ethernet peripheral nodes are located in stm32mp157cstm32mp151.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157cstm32mp151.dtsi | arch/arm/boot/dts/stm32mp157cstm32mp151.dtsi}}, STM32MP157CSTM32MP151 device tree file</ref> file with a disabled status and some required properties such as:
* Physical base address and size of the device register map
* STMMAC interrupts
* stmmaceth clock and Rx, Tx clocks

This is a set of properties that may not vary for a given STM32MP device, such as: register addresses, interrupts, clocks, ...
<pre>

ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_NONE>;
	interrupt-names = "macirq";
	clock-names = "stmmaceth",
		      "mac-clk-tx",
		      "mac-clk-rx",
		      "ethstp",
		      "syscfg-clk";
	clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>,<&rcc SYSCFG>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	power-domains = <&pd_core>;
	status = "disabled";
};</pre>


The required and optional properties are fully described in the [[Ethernet device tree configuration#DT bindings documentation|bindings files]].
{{Warning|This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.}}

=== Ethernet DT configuration (board level) ===

The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ('''"ethernet"''') should be updated to:

* Enable the Ethernet block by setting '''status = "okay".'''
* Configure the pins in use via [[Pinctrl overview|pinctrl]], through '''pinctrl-0''' (default pins), '''pinctrl-1''' (sleep pins) and '''pinctrl-names'''.
* Configure Ethernet interface used '''phy-mode = "rgmii".''', (rmii, mii, gmii).
* Configure Ethernet max speed '''max-speed = <1000>".'''.
<pre>

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@1 {
			reg = <1>;
		};
	};
};</pre>


=== DT configuration examples ===
The example below shows how to configure and enable an Ethernet instance at board level:

 &ethernet0 {
    status = "okay";                             {{highlight|/* enable ethernet0 */}} 
    pinctrl-0 = <&ethernet0_rmii_pins_a>;        {{highlight|/* configure pinctrl modes for ethernet0 */}}
    pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;  {{highlight|/* configure ethernet0_rmii_pins_sleep_a as sleep pinctrl configuration for ethernet0 */}}
    pinctrl-names = "default", "sleep";
    phy-mode = "rmii";                           {{highlight|/* configure ethernet phy mode for ethernet0 */}}
    max-speed = <100>;                           {{highlight|/* configure ethernet max speed for ethernet0 */}}
    phy-handle = <&phy0>;

    mdio0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "snps,dwmac-mdio";
        phy0: ethernet-phy@1 {
            reg = <1>;                           {{highlight|/* configure ethernet phy @ for ethernet0 */}}
        };
    };
 };
== How to configure Ethernet for :
==== RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal) ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,<&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

==== RMII with 25MHz on ETH_CLK (no PHY Crystal), REF_CLK from PHY (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock) ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      '''"eth-ck",'''
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,
                 '''<&rcc ETHCK_K>,'''                <&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi}}, STM32MP15 pinctrl device tree file</ref> to add ETHCK pin in ethernet0_rmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA devicetree to generate 25Mhz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 

 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  };

==== RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC  (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock) ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      '''"eth-ck",'''
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,
                 '''<&rcc ETHCK_K>,'''                <&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,eth_ref_clk_sel;'''               {{highlight|/* In case of U-Boot */}} 
       or
        '''st,eth-ref-clk-sel;'''               {{highlight|/* In case of Linux Kernel */}} 
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rmii";
        max-speed = <100>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */

+ Need also to update TFA to generate 50Mhz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 508.0 MHz => P = 50, Q = 60, R = 60 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
     '''cfg = < 1 49 11 9 9 PQR(1,1,1) >;'''
   };

==== RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal) ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,             <&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
    };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
            };
    };

==== RGMII with 25MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock) ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      '''"eth-ck",'''
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,
                 '''<&rcc ETHCK_K>,'''                <&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rgmii_pins_* node:<br>

For example:<STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */

+ Need also to update TFA to generate 25Mhz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi  
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
    pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  };

==== RGMII with Crystal on PHY, no 125Mhz from PHY ====

    ethernet0: ethernet@5800a000 {
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
        reg = <0x5800a000 0x2000>;
        reg-names = "stmmaceth";
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<&exti 70 1>;
        interrupt-names = "macirq",
                          "eth_wake_irq",
                          "stm32_pwr_wakeup";
        clock-names = "stmmaceth",
                      '''"eth-ck",'''
                      "mac-clk-tx",
                      "mac-clk-rx",
                      "ethstp";
        clocks = <&rcc ETHMAC>,
                 '''<&rcc ETHCK_K>,'''                <&rcc ETHTX>,<&rcc ETHRX>,<&rcc ETHSTP>;
        st,syscon = <&syscfg 0x4>;
        snps,mixed-burst;
        snps,pbl = <2>;
        snps,en-tx-lpi-clockgating;
        '''st,eth_clk_sel;'''               {{highlight|/* In case of U-Boot */}} 
       or
        '''st,eth-clk-sel;'''               {{highlight|/* In case of Linux Kernel */}} 
        snps,axi-config = <&stmmac_axi_config_0>;
        snps,tso;
        power-domains = <&pd_core>;
        status = "disabled";
 };

    &ethernet0 {
        status = "okay";
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
        pinctrl-names = "default", "sleep";
        phy-mode = "rgmii";
        max-speed = <1000>;
        phy-handle = <&phy0>;
        mdio0 {
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "snps,dwmac-mdio";
                phy0: ethernet-phy@0 {
                        reg = <0>;
                };
        };
    };

+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:<br>


+ Need also to update TFA to generate 125Mhz clock (from PLL4P or PLL3Q):<br>

for example if PLL4P in ed1 board:
update fdts/stm32mp15xx-edx.dtsi 
 st,pkcs = <
  CLK_CKPER_HSE
  CLK_FMC_ACLK
  CLK_QSPI_ACLK
  '''- CLK_ETH_DISABLED'''
  '''+ CLK_ETH_PLL4P'''
 ...
  /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
  pll4: st,pll@3 {
      compatible = "st,stm32mp1-pll";
      reg = <3>;
      '''cfg = < 3 124 5 11 11 PQR(1,1,1) >;'''
  };

=== DT configuration to reset Phy with GPIO ===
The example below shows how to configure GPIO to reset the Ethernet PHY.<br>

This chapter is applicable for custom board where the Ethernet PHY reset signal is connected to a GPIO. <br>

'''IMPORTANT''', for STMicroelectronics boards it is not possible to use this configuration because there is no dedicated GPIO to reset PHY.

For kernel update see "reset-gpios" in
Documentation/devicetree/bindings/net/ethernet-phy.yaml<ref>https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ethernet-phy.yaml, More information</ref> <br>


  &ethernet0 {
       status = "okay";
       pinctrl-0 = <&ethernet0_rgmii_pins_a>;
       pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
       pinctrl-names = "default", "sleep";
       phy-mode = "rgmii";
       max-speed = <1000>;
       phy-handle = <&phy0>;
       mdio0 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "snps,dwmac-mdio";
               phy0: ethernet-phy@0 {
                        reg = <0>;
                        reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
                        reset-assert-us = <1000>;
                        reset-deassert-us = <2000>;
               };
       };
  };

For U-Boot same syntax of kernel, except that "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so you can change these value in function eqos_start_resets_stm32 of file dwc_eth_qos.c<ref>https://github.com/u-boot/u-boot/blob/master/drivers/net/dwc_eth_qos.c, More information</ref> 


== How to configure Ethernet using CubeMX ==
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32|platform configuration device tree]] files.<br />

The STM32CubeMX may not support all the properties described in the above [[#DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.

==References==<references />

<noinclude>

[[Category:Device tree configuration]]
[[Category:Ethernet]]
{{PublicationRequestId | 10170 | 2019-01-02 | BrunoB}}
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}</noinclude>
(37 intermediate revisions by 3 users not shown)
Line 1: Line 1:
<noinclude>
 
{{ArticleBasedOnModel | [[Peripheral or framework device tree configuration model]]}}
 
{{ArticleMainWriter | ChristopheR}}
 
{{ArticleApprovedVersion| ChristopheR | AlexandreT (Not Done), GeraldB (Not Done), ErwanL (Not Done), LoicP (KO W846)| No previous approved version | BrunoB - 02Jan'19 - 10170 | 14Jan'19}}
 
 
[[Category:Device tree configuration]]
 
[[Category:Ethernet]]
 
</noinclude>
 
 
 
== Article purpose ==
 
== Article purpose ==
 
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the [[Ethernet overview|Ethernet framework]]
 
This article explains how to configure the [[ETH internal peripheral|Ethernet]] when it is assigned to the Linux<sup>&reg;</sup> OS. In that case, it is controlled by the [[Ethernet overview|Ethernet framework]]
Line 25: Line 16:
 
=== DT configuration (STM32 level) ===
 
=== DT configuration (STM32 level) ===
   
Ethernet peripheral nodes are located in stm32mp157c.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp157c.dtsi | arch/arm/boot/dts/stm32mp157c.dtsi}}, STM32MP157C device tree file</ref> file with a disabled status and some required properties such as:
+
Ethernet peripheral nodes are located in stm32mp151.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp151.dtsi | arch/arm/boot/dts/stm32mp151.dtsi}}, STM32MP151 device tree file</ref> file with a disabled status and some required properties such as:
 
* Physical base address and size of the device register map
 
* Physical base address and size of the device register map
 
* STMMAC interrupts
 
* STMMAC interrupts
Line 42: Line 33:
 
      "mac-clk-tx",
 
      "mac-clk-tx",
 
      "mac-clk-rx",
 
      "mac-clk-rx",
      "ethstp",
+
      "ethstp";
      "syscfg-clk";
 
 
clocks = <&rcc ETHMAC>,
 
clocks = <&rcc ETHMAC>,
 
<&rcc ETHTX>,
 
<&rcc ETHTX>,
 
<&rcc ETHRX>,
 
<&rcc ETHRX>,
<&rcc ETHSTP>,
+
<&rcc ETHSTP>;
<&rcc SYSCFG>;
 
 
st,syscon = <&syscfg 0x4>;
 
st,syscon = <&syscfg 0x4>;
 
snps,mixed-burst;
 
snps,mixed-burst;
Line 113: Line 102:
 
     };
 
     };
 
  };
 
  };
  +
  +
How to configure Ethernet for :
  +
==== RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal) ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
};
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rmii";
  +
        max-speed = <100>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
        };
  +
    };
  +
  +
==== RMII with 25MHz on ETH_CLK (no PHY Crystal), REF_CLK from PHY (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock) ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      '''"eth-ck",'''
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,
  +
                '''<&rcc ETHCK_K>,'''               
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
};
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rmii";
  +
        max-speed = <100>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
        };
  +
    };
  +
  +
+ update stm32mp15-pinctrl.dtsi <ref>{{CodeSource | Linux kernel | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | arch/arm/boot/dts/stm32mp15-pinctrl.dtsi}}, STM32MP15 pinctrl device tree file</ref> to add ETHCK pin in ethernet0_rmii_pins_* node:<br>
  +
For example:
  +
  <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */
  +
  +
+ Need also to update TFA devicetree to generate 25Mhz clock (from PLL4P or PLL3Q):<br>
  +
for example if PLL4P in ed1 board:
  +
update fdts/stm32mp15xx-edx.dtsi
  +
  +
st,pkcs = <
  +
  CLK_CKPER_HSE
  +
  CLK_FMC_ACLK
  +
  CLK_QSPI_ACLK
  +
  '''- CLK_ETH_DISABLED'''
  +
  '''+ CLK_ETH_PLL4P'''
  +
...
  +
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
  +
    pll4: st,pll@3 {
  +
      compatible = "st,stm32mp1-pll";
  +
      reg = <3>;
  +
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  +
  };
  +
  +
==== RMII with 50MHz on ETH_CLK (no PHY Crystal), internal REF_CLK from RCC  (Reference clock (standard RMII clock name) is provided by a RCC SoC internal clock) ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      '''"eth-ck",'''
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,
  +
                '''<&rcc ETHCK_K>,'''               
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        '''st,eth_ref_clk_sel;'''              {{highlight|/* In case of U-Boot */}}
  +
      or
  +
        '''st,eth-ref-clk-sel;'''              {{highlight|/* In case of Linux Kernel */}}
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
};
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rmii";
  +
        max-speed = <100>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
        };
  +
    };
  +
  +
+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rmii_pins_* node:<br>
  +
For example:
  +
  <STM32_PINMUX('G', 8, AF2)>, /* ETH_RMII_ETHCK */
  +
  +
+ Need also to update TFA to generate 50Mhz clock (from PLL4P or PLL3Q):<br>
  +
for example if PLL4P in ed1 board:
  +
update fdts/stm32mp15xx-edx.dtsi
  +
st,pkcs = <
  +
  CLK_CKPER_HSE
  +
  CLK_FMC_ACLK
  +
  CLK_QSPI_ACLK
  +
  '''- CLK_ETH_DISABLED'''
  +
  '''+ CLK_ETH_PLL4P'''
  +
...
  +
  /* VCO = 508.0 MHz => P = 50, Q = 60, R = 60 */
  +
    pll4: st,pll@3 {
  +
      compatible = "st,stm32mp1-pll";
  +
      reg = <3>;
  +
    '''cfg = < 1 49 11 9 9 PQR(1,1,1) >;'''
  +
  };
  +
  +
==== RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal) ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,           
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
    };
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rgmii";
  +
        max-speed = <1000>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
            };
  +
    };
  +
  +
==== RGMII with 25MHz on ETH_CLK (no PHY Crystal), CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a RCC SoC internal clock) ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      '''"eth-ck",'''
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,
  +
                '''<&rcc ETHCK_K>,'''               
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
};
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rgmii";
  +
        max-speed = <1000>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
        };
  +
    };
  +
  +
+ update stm32mp15-pinctrl.dtsi to add ETHCK pin in ethernet0_rgmii_pins_* node:<br>
  +
For example:
  +
  <STM32_PINMUX('G', 8, AF2)>, /* ETH_RGMII_ETHCK */
  +
  +
+ Need also to update TFA to generate 25Mhz clock (from PLL4P or PLL3Q):<br>
  +
for example if PLL4P in ed1 board:
  +
update fdts/stm32mp15xx-edx.dtsi 
  +
st,pkcs = <
  +
  CLK_CKPER_HSE
  +
  CLK_FMC_ACLK
  +
  CLK_QSPI_ACLK
  +
  '''- CLK_ETH_DISABLED'''
  +
  '''+ CLK_ETH_PLL4P'''
  +
...
  +
  /* VCO = 600.0 MHz => P = 25, Q = 50, R = 50 */
  +
    pll4: st,pll@3 {
  +
      compatible = "st,stm32mp1-pll";
  +
      reg = <3>;
  +
      '''cfg = < 1 49 23 11 11 PQR(1,1,1) >;'''
  +
  };
  +
  +
==== RGMII with Crystal on PHY, no 125Mhz from PHY ====
  +
  +
    ethernet0: ethernet@5800a000 {
  +
        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  +
        reg = <0x5800a000 0x2000>;
  +
        reg-names = "stmmaceth";
  +
        interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  +
                              <&exti 70 1>;
  +
        interrupt-names = "macirq",
  +
                          "eth_wake_irq",
  +
                          "stm32_pwr_wakeup";
  +
        clock-names = "stmmaceth",
  +
                      '''"eth-ck",'''
  +
                      "mac-clk-tx",
  +
                      "mac-clk-rx",
  +
                      "ethstp";
  +
        clocks = <&rcc ETHMAC>,
  +
                '''<&rcc ETHCK_K>,'''               
  +
                <&rcc ETHTX>,
  +
                <&rcc ETHRX>,
  +
                <&rcc ETHSTP>;
  +
        st,syscon = <&syscfg 0x4>;
  +
        snps,mixed-burst;
  +
        snps,pbl = <2>;
  +
        snps,en-tx-lpi-clockgating;
  +
        '''st,eth_clk_sel;'''              {{highlight|/* In case of U-Boot */}}
  +
      or
  +
        '''st,eth-clk-sel;'''              {{highlight|/* In case of Linux Kernel */}}
  +
        snps,axi-config = <&stmmac_axi_config_0>;
  +
        snps,tso;
  +
        power-domains = <&pd_core>;
  +
        status = "disabled";
  +
};
  +
  +
    &ethernet0 {
  +
        status = "okay";
  +
        pinctrl-0 = <&ethernet0_rgmii_pins_a>;
  +
        pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
  +
        pinctrl-names = "default", "sleep";
  +
        phy-mode = "rgmii";
  +
        max-speed = <1000>;
  +
        phy-handle = <&phy0>;
  +
        mdio0 {
  +
                #address-cells = <1>;
  +
                #size-cells = <0>;
  +
                compatible = "snps,dwmac-mdio";
  +
                phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                };
  +
        };
  +
    };
  +
  +
+ update stm32mp15-pinctrl.dtsi to delete CLK125 pin (also no need of ETHCK pin) in ethernet0_rgmii_pins_* node:<br>
  +
  +
+ Need also to update TFA to generate 125Mhz clock (from PLL4P or PLL3Q):<br>
  +
for example if PLL4P in ed1 board:
  +
update fdts/stm32mp15xx-edx.dtsi
  +
st,pkcs = <
  +
  CLK_CKPER_HSE
  +
  CLK_FMC_ACLK
  +
  CLK_QSPI_ACLK
  +
  '''- CLK_ETH_DISABLED'''
  +
  '''+ CLK_ETH_PLL4P'''
  +
...
  +
  /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
  +
  pll4: st,pll@3 {
  +
      compatible = "st,stm32mp1-pll";
  +
      reg = <3>;
  +
      '''cfg = < 3 124 5 11 11 PQR(1,1,1) >;'''
  +
  };
  +
  +
=== DT configuration to reset Phy with GPIO ===
  +
The example below shows how to configure GPIO to reset the Ethernet PHY.<br>
  +
This chapter is applicable for custom board where the Ethernet PHY reset signal is connected to a GPIO. <br>
  +
'''IMPORTANT''', for STMicroelectronics boards it is not possible to use this configuration because there is no dedicated GPIO to reset PHY.
  +
  +
For kernel update see "reset-gpios" in
  +
Documentation/devicetree/bindings/net/ethernet-phy.yaml<ref>https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ethernet-phy.yaml, More information</ref> <br>
  +
  +
  &ethernet0 {
  +
      status = "okay";
  +
      pinctrl-0 = <&ethernet0_rgmii_pins_a>;
  +
      pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
  +
      pinctrl-names = "default", "sleep";
  +
      phy-mode = "rgmii";
  +
      max-speed = <1000>;
  +
      phy-handle = <&phy0>;
  +
      mdio0 {
  +
              #address-cells = <1>;
  +
              #size-cells = <0>;
  +
              compatible = "snps,dwmac-mdio";
  +
              phy0: ethernet-phy@0 {
  +
                        reg = <0>;
  +
                        reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
  +
                        reset-assert-us = <1000>;
  +
                        reset-deassert-us = <2000>;
  +
              };
  +
      };
  +
  };
  +
  +
For U-Boot same syntax of kernel, except that "reset-assert-us" and "reset-deassert-us" properties which are not managed (values of this properties are hardcoded in driver (udelay(2)), so you can change these value in function eqos_start_resets_stm32 of file dwc_eth_qos.c<ref>https://github.com/u-boot/u-boot/blob/master/drivers/net/dwc_eth_qos.c, More information</ref>
   
 
== How to configure Ethernet using CubeMX ==
 
== How to configure Ethernet using CubeMX ==
Line 120: Line 526:
 
==References==
 
==References==
 
<references />
 
<references />
  +
  +
<noinclude>
  +
[[Category:Device tree configuration]]
  +
[[Category:Ethernet]]
  +
{{PublicationRequestId | 10170 | 2019-01-02 | BrunoB}}
  +
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}}
  +
</noinclude>