TF-A - Flash memory configuration

1. Article purpose

This article explains how to configure the QUADSPI internal peripheral and FMC internal peripheral connected to a flash device when it is assigned to the TF-A BL2. In that case, it is controlled by new TF-A frameworks:

• SPI NOR
• SPI NAND
• SPI MEM
• FMC NAND

These frameworks represents the memory access organisation.

These frameworks use two different configurations:

• Device tree configuration
• Boot device configuration

If the peripheral is assigned to another execution context, refer to How to assign an internal peripheral to a runtime context article for guidelines on peripheral assignment and configuration.

2. Framework overview

2.1. Components description

• IO_Storage

The IO storage provides an abstraction layer to access storage devices.

• Boot device configuration

The Boot device configuration is a platform specific ad-dons to specify memory specific settings.

• MTD core

The MTD core provides an abstraction layer for raw Flash memories.

• Raw NAND subsystem

The Raw NAND protocol is used in the MTD subsystem for interfacing NAND Flash memories.

• SPI-MEM subsystem

The SPI-MEM protocol is used in the MTD subsystem for interfacing all kinds of SPI memories (NORs, NANDs)

• SPI-NAND subsystem

The SPI-NAND protocol is used in the MTD subsystem for interfacing SPI NAND Flash memories.

• SPI-NOR subsystem

The SPI-NOR protocol is used in the MTD subsystem for interfacing SPI NOR Flash memories.

• FMC driver / FMC (Hardware)

Please refer to the FMC internal peripheral.

• QUADSPI driver / QUADSPI (Hardware)

Please refer to the QUADSPI internal peripheral.

3. DT configuration

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.

Pinctrl device tree configuration (and optionally to Pinctrl overview) must be added in #DT configuration (board level).

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

4. Raw NAND Flash memory

4.1. Raw NAND DT configuration

For the DT bindings, refers to FMC_device_tree_configuration.

For the DT configuration (STM32 level), refers to FMC DT Configuration at STM32 level.

For the DT configuration (board level), refers to FMC DT Configuration at board level.

Warning

Only the required device used to load images must be declared as a child node

4.2. Raw NAND device configuration

Raw NAND access will use the MTD Core and raw NAND framework. Some additional parameters are required by the raw NAND framework to address the memory:

• Page size
• Block size
• Blocks number in device
• NAND width (8 or 16 bits)
• ECC : Supported algorithm (BCH8/BCH4/Hamming are available). The default ECC framework configuration is no error correction.

Some memories are ONFI compliant. In that case, required parameters can be directly read from the parameter description table.

For the others, user must properly fill out OTP configuration.

4.2.1. Raw NAND examples

• 8bit NAND with 4KB paged / 256KB erase size / 1024MB size, ECC BCH8

OTP Word 9 : 0xA0818000

Param in OTP	Page size		Block size		Block numbers (N * 256)								Width	ECC
1	0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0

• Raw Nand ONFI with ECC override (Default from parameter table is BCH8, force to BCH4).

OTP Word 9 : 0x8000

Param in OTP	Page size		Block size		Block numbers (N * 256)								Width	ECC
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0

• 16bit NAND with 2KB paged / 512KB erase size / 2048MB size, with On die ECC

OTP Word 9 : 0x91060000

Param in OTP	Page size		Block size		Block numbers (N * 256)								Width	ECC
1	0	0	1	0	0	0	1	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

5. SPI NAND Flash memory

5.1. SPI NAND DT configuration

For the DT bindings, refers to the QUADSPI_device_tree_configuration.

For the DT configuration (STM32 level), refers to QUADSPI DT Configuration at STM32 level.

For the DT configuration (board level), refers to QUADSPI DT Configuration at board level.

Warning

Only the required device used to load images must be declared as a child node

5.2. SPI NAND device configuration

SPI NAND and SPI MEM frameworks are used to address such memories.

• SPI NAND framework required additional parameters:
  • Page size
  • Block size
  • Blocks number in device
  • Plane number

These parameters must be properly filled out by user in OTP configuration.

• SPI MEM framework is used to send commands.

By default, the generic read command used is the legacy command:
0x03 with 1 line command, 1 line address, 1 data bus width (1_1_1). It is possible to override this read command to improve performance access to the memory using platform configuration.

5.2.1. SPI NAND examples

• SPI NAND with 2KB paged / 256KB erase size / 1024MB size, 2 Planes

OTP Word 9 : 0x88804000

Param in OTP	Page size		Block size		Block numbers (N * 256)								Not Used	Not Used			2 Planes
1	0	0	0	1	0	0	0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0

• Update read command to use command 0x6B (1_1_4) define in platform file

device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X;
device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
device->spi_read_cache_op.addr.nbytes = 2U;
device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
device->spi_read_cache_op.dummy.nbytes = 1U;
device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN;

5.4. SPI NOR DT configuration

For the DT bindings, refers to the QUADSPI_device_tree_configuration.

For the DT configuration (STM32 level), refers to QUADSPI DT Configuration at STM32 level.

For the DT configuration (board level), refers to QUADSPI DT Configuration at board level.

Warning

Only the required device used to load images must be declared as a child node

5.5. SPI NOR memory configuration

SPI NOR and SPI MEM frameworks are used to address such memories.

• SPI NOR framework required additional parameters:
  • Device size

This parameters need to be defined in the platform configuration file<ref_name="boot_device">.

• SPI MEM framework is used to send commands.

By default, the generic read command used is the legacy command:
0x03 with 1 line command, 1 line address, 1 data bus width (1_1_1). It is possible to override this read command to improve performance access to the memory using platform configuration.

5.5.1. SPI NOR examples

• SPI NOR 64MB size

	device->size = SZ_64M;                                --> Device size

• Update read command to use command 0x6B (1_1_4) define in platform file

	device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4;
	device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
	device->read_op.addr.nbytes = 3U;
	device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
	device->read_op.dummy.nbytes = 1U;
	device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
	device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
	device->read_op.data.dir = SPI_MEM_DATA_IN;

6. How to configure the DT using STM32CubeMX

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

7. References

Please refer to the following links for additional information:

Trusted Firmware for Arm Cortex-A

Boot Loader stage 2

Serial Peripheral Interface

input/output

Memory Technology Device

Flash memory shortened to gain space in titles, tables and block diagrams

Device Tree

Flash memories combine high density and cost effectiveness of EPROMs with the electrical erasability of EEPROMs. For this reason, the Flash memory market is one of the most exciting areas of the semiconductor industry today and new applications requiring in system reprogramming, such as cellular telephones, automotive engine management systems, hard disk drives, PC BIOS software for Plug & Play, digital TV, set top boxes, fax and other modems, PC cards and multimedia CD-ROMs, offer the prospect of very high volume demand.

Elliptic curve cryptography

Error Correction Capability

Open NAND Flash interface (The ONFI working group, acronym for Open NAND Flash Interface, was founded in 2005. The group’s mission consists in creating a common industry standard for NAND Flash interfaces, to simplify integration of NAND Flash memory into consumer electronics (CE) devices and computing platforms. ST is one of the co-founder companies together with Hynix, Intel, Micron, Phison and Sony.)

One Time Programmed