TF-A - Flash memory configuration

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1. Article purpose[edit source]

This article explains how to configure the QUADSPI internal peripheral and FMC internal peripheral connected to a flash device when it is assigned to the TF-A BL2. In that case, it is controlled by a new TF-A framework. This framework support:

SPI NOR devices
SLC NAND devices
SPI NAND devices

The configuration is performed using the device tree mechanism that provides a hardware description of the FMC and QSPI peripheral. It also needs some platform specific description for flash memory optimization.

The memory devices configuration also required some specific configuration Software configuration:

SLC NAND : Device configuration for non-ONFI devices.
SPI NOR/NAND : Bus supported command.

If the peripheral is assigned to another execution context, refer to How to assign an internal peripheral to a runtime context article for guidelines on peripheral assignment and configuration.

2. DT bindings documentation[edit source]

It shares the same bindings as LInux kernel with some device limitation.

TF-A device tree only allow using a single device node per controller. It could be on the first or second chip select, but only the boot one must be declared.
All the properties are not used by TF-A.

2.1. NAND Flash memory[edit source]

Refers to FMC_device_tree_configuration.

Warning

The algorithm choice is not manage at device tree level for TF-A. For non-ONFI memories, a hardware configuration must be done, described in Rom code Overview

.

2.2. SPI NOR/NAND Flash memory[edit source]

Please refer to the QUADSPI_device_tree_configuration.

3. DT configuration[edit source]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.

Pinctrl device tree configuration (and optionally to Pinctrl overview) must be added in #DT configuration (board level).

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1. DT configuration (STM32 level)[edit source]

3.1.1. QUADSPI node[edit source]

Refers to QUADSPI DT Configuration at STM32 level|.

3.1.2. FMC node[edit source]

Refers to FMC DT Configuration at STM32 level.

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2. DT configuration (board level)[edit source]

As previously explained, only one device attached to a memory controller must be defined at board level. This device is the one used to locate the next boot stage. (BL32 and BL33 stages).

Refers to [[|QUADSPI_device_tree_configuration#DT_configuration_-28board_level-29|QUADSPI DT Configuration at board level]].

Refers to FMC DT Configuration at board level.

3.3. DT configuration examples[edit source]

3.3.1. QUASPI configuration[edit source]

The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash memory is connected and used as boot device.

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

       flash0: mt29f2g01abagd@0 {
           compatible = "spi-nand";
           reg = <0>;
           spi-rx-bus-width = <4>;
           spi-tx-bus-width = <4>;
           spi-max-frequency = <133000000>;
           #address-cells = <1>;
           #size-cells = <1>;
       };
};

3.3.2. FMC configuration[edit source]

The below example shows how to configure the FMC controller when a SLC 8-bit NAND Flash memory device is connected.

&fmc {
	pinctrl-names = "default";
	pinctrl-0 = <&fmc_pins_a>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	nand@0 {
		reg = <0>;
		nand-on-flash-bbt;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

4. How to configure the DT using STM32CubeMX[edit source]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5. Software configuration[edit source]

Because the TF-A framework is smaller than the Linux OS one, some configuration need to be defined inside the software.

5.1. SLC NAND Flash memory[edit source]

Some SLC NAND Flash memory doesn't provide the ONFI description table. Some properties must be set into the hardware to allow TF-A framework properly read the device. STM32MP15 TF-A platform reuses the Rom Code properties to find the correct settings. This settings are parsed in a platform device function.^[1].

5.2. QUADSPI NOR/NAND Flash memory[edit source]

Memories over SPI bus are using some specific bus parameters. The standard one (legacy mode) is coded inside the framework ^[2]. It is also possible to override these default settings using the platform functions.^[3] There are two different functions, one for NOR device, one for SPI nand devices.

6. References[edit source]

Please refer to the following links for additional information:

[1] t/st/stm32mp1/stm32mp1_boot_device.c

[2] rivers/mtd/nor/spi_nor.c

[3] t/st/stm32mp1/stm32mp1_boot_device.c

[1]

[2]

[3]