1. Article purpose[edit source]
This article explains how to configure the DDRCTRL and DDRPHYC internal peripheral done by the first stage bootloader.
The configuration is performed using the device tree mechanism that provides a hardware description of the DDR subsystem (DDR controler and DDR PHY peripheral), used by the first stage bootloader to initialize the DDR before to load second stage bootloader.
The DDR settings are only used in the device tree of the boot chain FSBL; so in the TF-A device tree for OpenSTLinux official delivery (or in SPL only for the DDR tuning tool).
Even if the DDR node information is also present in the U-Boot device tree, it is not used during boot by this SSBL.
2. DT bindings documentation[edit source]
The DDR sub system is a memory-controllers device represented by the device tree bindings.
The following binding-related documentation explains how to write device tree files for DDR subsystem:
- TF-A: docs/devicetree/bindings/memory-controllers/st,stm32mp1-ddr.txt"[1]
- U-Boot: doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.tx"[2]
3. DT configuration[edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
STM32CubeMX can be used to generate this DDR board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)[edit source]
The STM32MP1 DDR node is located in stm32mp15-ddr.dtsi' '[3] (see Device tree for further explanation).
/ {
soc {
u-boot,dm-spl;
ddr: ddr@0x5A003000{
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
clocks = <&rcc_clk AXIDCG>,
<&rcc_clk DDRC1>,
<&rcc_clk DDRC2>,
<&rcc_clk DDRPHYC>,
<&rcc_clk DDRCAPB>,
<&rcc_clk DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
.....
status = "okay";
};
};
};
3.2. DT configuration (board level)[edit source]
The next attributes the DDR settings, the register values used to inialized the DDR controller and the DDR PHY, they are generated by DDR tools included in STM32 Cube MX.
3.2.1. info attributes[edit source]
Just strings to identify the configuraiton:
- st,mem-name: name for DDR configuration, simple string for information
- st,mem-speed: DDR expected speed for the setting in kHz
- st,mem-size: DDR mem size in byte
3.2.2. controllor attributes[edit source]
- st,ctl-reg: controleur values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
- for STM32MP1 Series: 25 values are requested in this order
- for STM32MP1 Series: 25 values are requested in this order
MSTR, MRCTRL0, MRCTRL1, DERATEEN, DERATEINT, PWRCTL, PWRTMG, HWLPCTL, RFSHCTL0
RFSHCTL3, CRCPARCTL0, ZQCTL0, DFITMG0, DFITMG1, DFILPCFG0, DFIUPD0, DFIUPD1, DFIUPD2
DFIPHYMSTR, ODTMAP, DBG0, DBG1, DBGCMD, POISONCFG, PCCFG
- st,ctl-timing: controleur values depending of frequency and timing parameter of DDR
- for STM32MP15x lines
: 12 values are requested in this order
- for STM32MP15x lines
RFSHTMG DRAMTMG0 DRAMTMG1 DRAMTMG2 DRAMTMG3 DRAMTMG4 DRAMTMG5 DRAMTMG6
DRAMTMG7 DRAMTMG8 DRAMTMG14 ODTCFG
- st,ctl-map: controleur values depending of address mapping
- for STM32MP15x lines : 9 values are requested in this order
- for STM32MP15x lines
ADDRMAP1 ADDRMAP2 ADDRMAP3 ADDRMAP4 ADDRMAP5 ADDRMAP6 ADDRMAP9 ADDRMAP10 ADDRMAP11
- st,ctl-perf: controleur values depending of performance and scheduling
- for STM32MP15x lines : 17 values are requested in this order
- for STM32MP15x lines
SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0
PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 PCFGR_1 PCFGW_1 PCFGQOS0_1
PCFGQOS1_1 PCFGWQOS0_1 PCFGWQOS1_1
3.2.3. phy attributes[edit source]
- st,phy-reg: phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
- for STM32MP15x lines : 11 values are requested in this order
- for STM32MP15x lines
PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR DX2GCR DX3GCR
- st,phy-timing : phy values depending of frequency and timing parameter of DDR
- for STM32MP15x lines : 10 values are requested in this order
- for STM32MP15x lines
PTR0 PTR1 PTR2 DTPR0 DTPR1 DTPR2 MR0 MR1 MR2 MR3
- st,phy-cal : phy cal depending of calibration or tuning of DDR
- for STM32MP15x lines : 12 values are requested in this order
- for STM32MP15x lines
DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR DX2DLLCR DX2DQTR DX2DQSTR
DX3DLLCR DX3DQTR DX3DQSTR
The board configuration defines each needed configuration (DDR_...) and include the STM32 level device tree.
3.3. DT configuration examples[edit source]
/ {
st,mem-name = "DDR3 2x4Gb 533MHz";
st,mem-speed = <533000>;
st,mem-size = <0x40000000>;
st,ctl-reg = <
0x00040401 /*MSTR*/
0x00000010 /*MRCTRL0*/
0x00000000 /*MRCTRL1*/
0x00000000 /*DERATEEN*/
0x00800000 /*DERATEINT*/
0x00000000 /*PWRCTL*/
0x00400010 /*PWRTMG*/
0x00000000 /*HWLPCTL*/
0x00210000 /*RFSHCTL0*/
0x00000000 /*RFSHCTL3*/
0x00000000 /*CRCPARCTL0*/
0xC2000040 /*ZQCTL0*/
0x02050105 /*DFITMG0*/
0x00000202 /*DFITMG1*/
0x07000000 /*DFILPCFG0*/
0xC0400003 /*DFIUPD0*/
0x00000000 /*DFIUPD1*/
0x00000000 /*DFIUPD2*/
0x00000000 /*DFIPHYMSTR*/
0x00000001 /*ODTMAP*/
0x00000000 /*DBG0*/
0x00000000 /*DBG1*/
0x00000000 /*DBGCMD*/
0x00000000 /*POISONCFG*/
0x00000010 /*PCCFG*/
>;
st,ctl-timing = <
0x0080008A /*RFSHTMG*/
0x121B2414 /*DRAMTMG0*/
0x000D041B /*DRAMTMG1*/
0x0607080E /*DRAMTMG2*/
0x0050400C /*DRAMTMG3*/
0x07040407 /*DRAMTMG4*/
0x06060303 /*DRAMTMG5*/
0x02020002 /*DRAMTMG6*/
0x00000202 /*DRAMTMG7*/
0x00001005 /*DRAMTMG8*/
0x000D041B /*DRAMTMG1*/4
0x06000600 /*ODTCFG*/
>;
st,ctl-map = <
0x00080808 /*ADDRMAP1*/
0x00000000 /*ADDRMAP2*/
0x00000000 /*ADDRMAP3*/
0x00001F1F /*ADDRMAP4*/
0x07070707 /*ADDRMAP5*/
0x0F070707 /*ADDRMAP6*/
0x00000000 /*ADDRMAP9*/
0x00000000 /*ADDRMAP10*/
0x00000000 /*ADDRMAP11*/
>;
st,ctl-perf = <
0x00001201 /*SCHED*/
0x00001201 /*SCHED*/1
0x01000001 /*PERFHPR1*/
0x08000200 /*PERFLPR1*/
0x08000400 /*PERFWR1*/
0x00010000 /*PCFGR_0*/
0x00000000 /*PCFGW_0*/
0x02100B03 /*PCFGQOS0_0*/
0x00800100 /*PCFGQOS1_0*/
0x01100B03 /*PCFGWQOS0_0*/
0x01000200 /*PCFGWQOS1_0*/
0x00010000 /*PCFGR_1*/
0x00000000 /*PCFGW_1*/
0x02100B03 /*PCFGQOS0_1*/
0x00800000 /*PCFGQOS1_1*/
0x01100B03 /*PCFGWQOS0_1*/
0x01000200 /*PCFGWQOS1_1*/
>;
st,phy-reg = <
0x01442E02 /*PGCR*/
0x10400812 /*ACIOCR*/
0x00000C40 /*DXCCR*/
0xF200001F /*DSGCR*/
0x0000000B /*DCR*/
0x00010000 /*ODTCR*/
0x0000007B /*ZQ0CR1*/
0x0000CE81 /*DX0GCR*/
0x0000CE81 /*DX1GCR*/
0x0000CE81 /*DX2GCR*/
0x0000CE81 /*DX3GCR*/
>;
st,phy-timing = <
0x0022A41B /*PTR0*/
0x047C0740 /*PTR1*/
0x042D9C80 /*PTR2*/
0x369477D0 /*DTPR0*/
0x098A00D8 /*DTPR1*/
0x10023600 /*DTPR2*/
0x00000830 /*MR0*/
0x00000000 /*MR1*/
0x00000208 /*MR2*/
0x00000000 /*MR3*/
>;
st,phy-cal = <
0x40000000 /*DX0DLLCR*/
0xFFFFFFFF /*DX0DQTR*/
0x3DB02000 /*DX0DQSTR*/
0x40000000 /*DX1DLLCR*/
0xFFFFFFFF /*DX1DQTR*/
0x3DB02000 /*DX1DQSTR*/
0x40000000 /*DX2DLLCR*/
0xFFFFFFFF /*DX2DQTR*/
0x3DB02000 /*DX2DQSTR*/
0x40000000 /*DX3DLLCR*/
0xFFFFFFFF /*DX3DQTR*/
0x3DB02000 /*DX3DQSTR*/
>;
};
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45" #define DDR_MEM_SPEED 533000 #define DDR_MEM_SIZE 0x20000000 #define DDR_MSTR 0x00041401 #define DDR_MRCTRL0 0x00000010 #define DDR_MRCTRL1 0x00000000 #define DDR_DERATEEN 0x00000000 #define DDR_DERATEINT 0x00800000 #define DDR_PWRCTL 0x00000000 #define DDR_PWRTMG 0x00400010 #define DDR_HWLPCTL 0x00000000 #define DDR_RFSHCTL0 0x00210000 #define DDR_RFSHCTL3 0x00000000 #define DDR_RFSHTMG 0x0081008B #define DDR_CRCPARCTL0 0x00000000 #define DDR_DRAMTMG0 0x121B2414 #define DDR_DRAMTMG1 0x000A041C #define DDR_DRAMTMG2 0x0608090F #define DDR_DRAMTMG3 0x0050400C #define DDR_DRAMTMG4 0x08040608 #define DDR_DRAMTMG5 0x06060403 #define DDR_DRAMTMG6 0x02020002 #define DDR_DRAMTMG7 0x00000202 #define DDR_DRAMTMG8 0x00001005 #define DDR_DRAMTMG14 0x000000A0 #define DDR_ZQCTL0 0xC2000040 #define DDR_DFITMG0 0x02060105 #define DDR_DFITMG1 0x00000202 #define DDR_DFILPCFG0 0x07000000 #define DDR_DFIUPD0 0xC0400003 #define DDR_DFIUPD1 0x00000000 #define DDR_DFIUPD2 0x00000000 #define DDR_DFIPHYMSTR 0x00000000 #define DDR_ADDRMAP1 0x00070707 #define DDR_ADDRMAP2 0x00000000 #define DDR_ADDRMAP3 0x1F000000 #define DDR_ADDRMAP4 0x00001F1F #define DDR_ADDRMAP5 0x06060606 #define DDR_ADDRMAP6 0x0F060606 #define DDR_ADDRMAP9 0x00000000 #define DDR_ADDRMAP10 0x00000000 #define DDR_ADDRMAP11 0x00000000 #define DDR_ODTCFG 0x06000600 #define DDR_ODTMAP 0x00000001 #define DDR_SCHED 0x00000C01 #define DDR_SCHED1 0x00000000 #define DDR_PERFHPR1 0x01000001 #define DDR_PERFLPR1 0x08000200 #define DDR_PERFWR1 0x08000400 #define DDR_DBG0 0x00000000 #define DDR_DBG1 0x00000000 #define DDR_DBGCMD 0x00000000 #define DDR_POISONCFG 0x00000000 #define DDR_PCCFG 0x00000010 #define DDR_PCFGR_0 0x00010000 #define DDR_PCFGW_0 0x00000000 #define DDR_PCFGQOS0_0 0x02100C03 #define DDR_PCFGQOS1_0 0x00800100 #define DDR_PCFGWQOS0_0 0x01100C03 #define DDR_PCFGWQOS1_0 0x01000200 #define DDR_PCFGR_1 0x00010000 #define DDR_PCFGW_1 0x00000000 #define DDR_PCFGQOS0_1 0x02100C03 #define DDR_PCFGQOS1_1 0x00800040 #define DDR_PCFGWQOS0_1 0x01100C03 #define DDR_PCFGWQOS1_1 0x01000200 #define DDR_PGCR 0x01442E02 #define DDR_PTR0 0x0022AA5B #define DDR_PTR1 0x04841104 #define DDR_PTR2 0x042DA068 #define DDR_ACIOCR 0x10400812 #define DDR_DXCCR 0x00000C40 #define DDR_DSGCR 0xF200011F #define DDR_DCR 0x0000000B #define DDR_DTPR0 0x38D488D0 #define DDR_DTPR1 0x098B00D8 #define DDR_DTPR2 0x10023600 #define DDR_MR0 0x00000840 #define DDR_MR1 0x00000000 #define DDR_MR2 0x00000208 #define DDR_MR3 0x00000000 #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 #define DDR_DX0DLLCR 0x40000000 #define DDR_DX0DQTR 0xFFFFFFFF #define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 #define DDR_DX1DLLCR 0x40000000 #define DDR_DX1DQTR 0xFFFFFFFF #define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE80 #define DDR_DX2DLLCR 0x40000000 #define DDR_DX2DQTR 0xFFFFFFFF #define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE80 #define DDR_DX3DLLCR 0x40000000 #define DDR_DX3DQTR 0xFFFFFFFF #define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi"
4. How to configure the DT using STM32CubeMX[edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts all the needed defines in . Refer to STM32CubeMX user manual for further information.
See also How_to_create_your_board_device_tree#DDR configuration with STM32CubeMX DDR Tuning Tool.
5. References[edit source]
Please refer to the following links for additional information:
- ↑ docs/devicetree/bindings/memory-controllers/st,stm32mp1-ddr.txt TF-A DDR binding information file
- ↑ doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt U-Boot DDR binding information file
- ↑ fdts/stm32mp15-ddr.dtsi (for TF-A): STM32MP157C device tree files