STM32MP15 ecosystem errata sheet

This article aims to describe what workarounds are implemented in STM32MP15-Ecosystem-v1.0.0 release, among the ones proposed in STM32MP15xx device errata .

Here is the legend for the column "Status" in the table below:

• A = workaround available
• N = no workaround available
• P = partial workaround available

Fly over the letters in the column to show it locally.

Function	Section	Limitation	Status Rev.B (fly over to show the legend)	Workaround implemented in STM32MP15 ecosystem
Arm Cortex-A7 core	2.1.1	Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set	A	None: STM32MPU Embedded Software distribution does not include any hypervisor, so this errata is not applicable
	2.1.2	Cache maintenance by set/way operations can execute out of order	A	None
	2.1.3	PMU events 0x07, 0x0C, and 0x0E do not increment correctly	N	None
	2.1.4	PMU event counter 0x14 does not increment correctly	A	None
	2.1.5	Exception mask bits are cleared when an exception is taken in Hyp mode	N	None: STM32MPU Embedded Software distribution does not include any hypervisor, so this errata is not applicable
Arm Cortex-M4 core	2.2.1	Interrupted loads to SP can cause erroneous behavior	A	None
	2.2.2	VDIV or VSQRT instructions might not complete correctly when very short ISRs are used	A	None: those instructions are not used in STM32CubeMP1 Package
	2.2.3	Store immediate overlapping exception return operation might vector to incorrect interrupt	A
System	2.3.1	TPIU fails to output sync after the pattern generator is disabled in Normal mode	A	None
	2.3.2	Serial-wire multi-drop debug not supported	N
	2.3.3	HSE external oscillator required in some LTDC use cases	P	External oscillator implemented on STM32MP157C-EV1 MB1263 Rev.C (aka "MB1263C") and STM32MP157X-DKX MB1272 Rev.C (aka "MB1272C")
	2.3.4	RCC cannot exit Stop and LP-Stop modes	A	Workaround implemented in TF-A plat/st/stm32mp1/bl2_plat_setup.c#L279
	2.3.5	Incorrect reset of glitch-free kernel clock switch	P	STPMIC1 performs a VDDCORE reset on NRST activation, by default
	2.3.6	Limitation of aclk/hclk5/hclk6 to 200 MHz when used as SDMMC1/2 kernel clock	P	Workaround implemented in TF-A fdts with a clock tree that uses a kernel clock source that is not the bus clock
DDRPHYC	2.4.1	DDRPHYC overconsumption upon reset or Standby mode exit	A	None
DMAMUX	2.5.1	SOFx not asserted when writing into DMAMUX_CFR register	N	Synchronization mode not used in OpenSTLinux distribution. None in STM32CubeMP1 Package.
	2.5.2	OFx not asserted for trigger event coinciding with last DMAMUX request	N	Trigger inputs not used in OpenSTLinux distribution. None in STM32CubeMP1 Package.
	2.5.3	OFx not asserted when writing into DMAMUX_RGCFR register	N	Trigger inputs (and so, request generator) not used in OpenSTLinux distribution. None in STM32CubeMP1 Package.
	2.5.4	Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event	A	Synchronization mode not used in OpenSTLinux distribution. None in STM32CubeMP1 Package.
QUADSPI	2.6.1	Memory-mapped read of last memory byte fails	P	Workaround implemented in OpenSTLinux distribution drivers/spi/spi-stm32-qspi.c#L452
ADC	2.7.1	ADC ANA0/ANA1 resolution limited when Gigabit Ethernet is used	P	None
	2.7.2	ADC missing codes in differential 16-bit static acquisition	P	None
DTS	2.8.1	Mode using PCLK & LSE (REFCLK_SEL = 1) should not be used	P	Workaround implemented in OpenSTLinux distribution drivers/thermal/st/stm_thermal.c#L215
DSI	2.9.1	DSI PHY compliant with MIPI DPHY v0.81 specification, not with DSI PHY v1.0	N	None
TIM	2.10.1	One-pulse mode trigger not detected in master-slave reset + trigger configuration	P	None
LPTIM	2.11.1	MCU may remain stuck in LPTIM interrupt when entering Stop mode	A	Interrupt not used in OpenSTLinux distribution. None in STM32CubeMP1 Package.
	2.11.2	MCU may remain stuck in LPTIM interrupt when clearing event flag	P	Interrupt not used in OpenSTLinux distribution. Workaround implemented in STM32CubeMP1 Package Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c#L1413
RTC and TAMP	2.12.1	Incorrect version register	N	None
	2.12.2	Calendar initialization may fail in case of consecutive INIT mode entry	A	Workaround implemented in OpenSTLinux distribution drivers/rtc/rtc-stm32.c#L276
	2.12.3	Alarm flag may be repeatedly set when the core is stopped in debug	N	None. OpenSTLinux distribution does not use the subsecond features.
I2C	2.13.1	Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period	P	Workaround implemented in TF-A fdts with a clock tree that uses a kernel clock source that is greater than 20MHz
	2.13.2	Spurious bus error detection in master mode	A
	2.13.3	Spurious master transfer upon own slave address match	P	None
SPI	2.14.1	Master data transfer stall at system clock much faster than SCK	A	SPI is disabled after each EOT in OpenSTLinux distribution drivers/spi/spi-stm32.c .
	2.14.2	Corrupted CRC return at non-zero UDRDET setting	P	Slave mode & CRC not supported in OpenSTLinux distribution.
	2.14.3	TXP interrupt occurring while SPI disabled	A	The driver ensures that all interrupts are disabled before the SPI is disabled in OpenSTLinux distribution drivers/spi/spi-stm32.c .
ETH	2.15.1	Incorrect L4 inverse filtering results for corrupted packets	N	None
	2.15.2	Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled	A	None
	2.15.3	Tx DMA may halt while fetching TSO header under specific conditions	A	None
	2.15.4	Spurious receive watchdog timeout interrupt	A	None
	2.15.5	Incorrect flexible PPS output interval under specific conditions	A	None
	2.15.6	Packets dropped in RMII 10Mbps mode due to fake dribble and CRC error	A	None
	2.15.7	ARP offload function not effective	A	ARP is disabled in OpenSTLinux distribution.

Power Management Unit (in STPMIC context) or Performance Monitoring Unit (in Arm Cortex-A context)

also known as

Low Power (MIPI^® Alliance DSI standard)

Direct Memory Access

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Low Speed External oscillator (STM32 clock source)

Display Serial Interface (MIPI^® Alliance standard)

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

Microcontroller Unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

low-power timer (STM32 specific)

Inter-Integrated Circuit (Bi-directional 2-wire bus standard for efficient inter-IC control.)

Serial Peripheral Interface

End Of Transmission (MIPI^® Alliance DSI standard)

Cyclic redundancy check calculation unit

Protocol used by the Internet Protocol, specifically IPv4, to map IP network addresses to the hardware addresses used by a data link protocol (https://en.wikipedia.org/wiki/Address_Resolution_Protocol)