STGEN internal peripheral

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1. Article purpose[edit source]

The purpose of this article is to:

briefly introduce the STGEN peripheral and its main features
indicate the level of security supported by this hardware block
explain how it can be allocated to the three runtime contexts and linked to the corresponding software components
explain, when necessary, how to configure the STGEN peripheral.

2. Peripheral overview[edit source]

The STGEN peripheral provides the reference clock used by the Arm^® Cortex^®-A7 generic timer for its counters, including the system tick generation.

It is clocked by ACLK (the AXI bus clock), so caution is needed when this clock is changed; otherwise the operating system (running on the Cortex-A7) might run with a varying reference clock.

2.1. Features[edit source]

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2. Security support[edit source]

The STGEN is a single-instance peripheral that can be accessed via the two following register sets:

STGENC for the control. That is, a secure port (under ETZPC control).
STGENR for the read-only access. That is, a non secure port.

3. Peripheral usage and associated software[edit source]

3.1. Boot time[edit source]

The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chains overview) once the clock tree is set up.

3.2. Runtime[edit source]

3.2.1. Overview[edit source]

Linux^® and OP-TEE use the Arm Cortex-A7 generic timer that gets its counter from the STGEN, but this is transparent at run time.

Hence there is no runtime allocation decision for this peripheral: both contexts are selected by default.

3.2.2. Software frameworks[edit source]

Domain	Peripheral	Software frameworks			Comment
Domain	Peripheral	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Core	STGEN	see comment	see comment		Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime

3.2.3. Peripheral configuration[edit source]

3.2.4. Peripheral assignment[edit source]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Core	STGEN	STGEN	✓	✓