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The STM32MP15xx device errata document[1] lists and explains the different device errata and explains associated workaround (SW and/or HW) if any.
This article aims to describe which workarounds are implemented in STM32MP15-Ecosystem-v1.0.0 release, among the ones proposed in STM32MP15xx device errata [1].
Here is the legend for the column "Status STM32MP15xx Rev.B" in the table below, which refers to the availability of a workaround for the described errata:
- A = workaround available
- P = partial workaround available
Here is the legend for the column "STM32MP15-Ecosystem-v1.0.0 Status" in the table below, which refers to the availability of a workaround in the STM32MP15-Ecosystem-v1.0.0 release:
- I = workaround Implemented
- P = workaround Partialy implemented
- N= workaround Not implemented
Fly over the letters in the columns to show legend locally.
| Function | Section | Limitation | Status STM32MP15xx Rev.B |
Status STM32MP15-Ecosystem-v1.0.0 |
Workaround implemented in STM32MP15 ecosystem |
|---|---|---|---|---|---|
| Arm® Cortex®-A7 core | 2.1.1 | Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set | A | N | Workaround not implemented: STM32MPU Embedded Software distribution does not activate Cortex®-A7 hypervisor mode and so Virtual Memory second stage of translation. It is customer responsibility to implement the workaround if hypervisor mode used in its product. |
| 2.1.2 | Cache maintenance by set/way operations can execute out of order | A | N | Limited impact on system. Implementation proposal under review at community level. Patch coming soon. | |
| 2.1.4 | PMU event counter 0x14 does not increment correctly | A | N | No impact on system. Minor impact performance measurement. No workaround provided by ARM for Linux kernel PMU driver. | |
| Arm® Cortex®-M4 core | 2.2.1 | Interrupted loads to SP can cause erroneous behavior | A | N | Limitation only on hand-written assembly code. Customer to implement workaround in its product assembly code. |
| 2.2.2 | VDIV or VSQRT instructions might not complete correctly when very short ISRs are used | A | N | STM32CubeMP1 Package provided as example. It is customer responsibility to implement one of the proposed workarounds according to its user code and product configuration. | |
| 2.2.3 | Store immediate overlapping exception return operation might vector to incorrect interrupt | A | N | Impact on system is minor. Workaround to be implemented by customer according to its MPU configuration. | |
| System | 2.3.1 | TPIU fails to output sync after the pattern generator is disabled in Normal mode | A | N | No workaround implemented. No impact on system, issue happens only trace port. |
| 2.3.3 | HSE external oscillator required in some LTDC use cases | P | I | HW implementation of external oscillator connected to the HSE pins available on STM32MP157C-EV1 MB1263 Rev.C (aka "MB1263C") and STM32MP157X-DKX MB1272 Rev.C (aka "MB1272C") HSE configuration implemented in TF-A fdts/stm32mp157c-ed1.dts for STM32MP157C-EV1 MB1263 and fdts/stm32mp157c-dk1.dts for STM32MP157X-DKX MB1272 | |
| 2.3.4 | RCC cannot exit Stop and LP-Stop modes | A | I | Implemented in TF-A plat/st/stm32mp1/bl2_plat_setup.c#L279 | |
| 2.3.5 | Incorrect reset of glitch-free kernel clock switch | P | I | STPMIC1 performs a VDDCORE reset on NRST activation, by default | |
| 2.3.6 | Limitation of aclk/hclk5/hclk6 to 200 MHz when used as SDMMC1/2 kernel clock | P | I | Implemented in TF-A fdts with a clock tree that uses a SDMMC1/SDMMC2 kernel clock source that is not the aclk/hclk5/hclk6 bus clock | |
| DDRPHYC | 2.4.1 | DDRPHYC overconsumption upon reset or Standby mode exit | A | P | DDRPHYC is correctly reinitialized by TF-A after reset and Standby mode exit. Issue remains in case of Cortex®-M4 standalone wake-up as TF-A not executed and so DDRPHYC not reinitialized in such case. |
| DMAMUX | 2.5.4 | Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event | A | P | Not applicable in OpenSTLinux distribution as DMA synchronous mode not used. Customer responsibility to provide the right DMAMUX signal polarity configuration when calling HAL_DMAEx_ConfigMuxSync() provided by STM32CubeMP1 PackageDrivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c#L320 . |
| QUADSPI | 2.6.1 | Memory-mapped read of last memory byte fails | P | A | Implemented in OpenSTLinux distribution drivers/spi/spi-stm32-qspi.c#L452 |
| ADC | 2.7.1 | ADC ANA0/ANA1 resolution limited when Gigabit Ethernet is used | P | P | Customer should implement workaround by limiting ADC data resolution in OpenSTLinux distribution device tree configuration or in its STM32CubeMP1 Package based application. |
| 2.7.2 | ADC missing codes in differential 16-bit static acquisition | P | P | Customer should implement workaround by limiting ADC data resolution in OpenSTLinux distribution device tree configuration or in its STM32CubeMP1 Package based application. | |
| DTS | 2.8.1 | Mode using PCLK & LSE (REFCLK_SEL = 1) should not be used | P | I | Implemented in OpenSTLinux distribution drivers/thermal/st/stm_thermal.c#L215 |
| TIM | 2.10.1 | One-pulse mode trigger not detected in master-slave reset + trigger configuration | P | N | Proposed workaround is only a recommendation |
| LPTIM | 2.11.1 | MCU may remain stuck in LPTIM interrupt when entering Stop mode | A | N | Interrupt not used in OpenSTLinux distribution. Workaround not implemented in STM32CubeMP1 Package. It is customer responsibility to implement it in MspDeinit(). |
| 2.11.2 | MCU may remain stuck in LPTIM interrupt when clearing event flag | P | I | Interrupt not used in OpenSTLinux distribution. Implemented in STM32CubeMP1 Package Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c#L1413 | |
| RTC and TAMP | 2.12.2 | Calendar initialization may fail in case of consecutive INIT mode entry | A | I | Implemented in OpenSTLinux distribution drivers/rtc/rtc-stm32.c#L276 |
| I2C | 2.13.1 | Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period | P | I | Implemented in TF-A fdts with a clock tree configuring I2C kernel clock source greater than 20MHz.
Valid for both OpenSTLinux distribution and STM32CubeMP1 Package. |
| 2.13.2 | Spurious bus error detection in master mode | A | N | Fix coming soon for OpenSTLinux distribution Workaround implemented in STM32CubeMP1 Package Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c | |
| 2.13.3 | Spurious master transfer upon own slave address match | P | P | Multi-mastering mode implementation of STM32CubeMP1 Package I2C HAL driver prevents to enter in such case. | |
| SPI | 2.14.1 | Master data transfer stall at system clock much faster than SCK | A | A | SPI is disabled after each EOT in OpenSTLinux distribution drivers/spi/spi-stm32.c and in STM32CubeMP1 Package Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c . |
| 2.14.2 | Corrupted CRC return at non-zero UDRDET setting | P | N | Slave mode & CRC not supported in OpenSTLinux distribution. Not implemented in STM32CubeMP1 Package. | |
| 2.14.3 | TXP interrupt occurring while SPI disabled | A | I | Implemented in OpenSTLinux distribution, drivers/spi/spi-stm32.c ensures that all interrupts are disabled before the SPI is disabled. Implemented in STM32CubeMP1 Package Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c . | |
| ETH | 2.15.2 | Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled | A | N | |
| 2.15.3 | Tx DMA may halt while fetching TSO header under specific conditions | A | N | ||
| 2.15.4 | Spurious receive watchdog timeout interrupt | A | N | ||
| 2.15.5 | Incorrect flexible PPS output interval under specific conditions | A | N | ||
| 2.15.6 | Packets dropped in RMII 10Mbps mode due to fake dribble and CRC error | A | N | ||
| 2.15.7 | ARP offload function not effective | A | P | Customer to activate ARP software support in OpenSTLinux distribution. |