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[[STM32CubeProgrammer]] can be used to read and update the OTP of the device which is seen as a partition on the device . | |||
[[ | This page describes the format of the partition used by embedded programming service to allow OTP access by STM32CubeProgrammer (see [[STM32MP15 resources#AN5275|AN5275: USB DFU/USART protocols used in STM32MP1 Series bootloaders]] for protocol details). | ||
[[STM32CubeProgrammer]] | Refer to [[STM32CubeProgrammer]] article to know how to use the STM32CubeProgrammer that is the official STMicroelectronics tool for update OTP on STM32 platforms. | ||
= OTP | == OTP partition == | ||
The OTP partition is identified by [[STM32CubeProgrammer_flashlayout#Field2:_Id | the reserved Id 0xF2]] and is exported as a specific alternate setting of the USB DFU <ref>https://en.wikipedia.org/wiki/USB#Device_Firmware_Upgrade</ref>. | The OTP partition is identified by [[STM32CubeProgrammer_flashlayout#Field2:_Id | the reserved Id 0xF2]] and is exported as a specific alternate setting of the USB DFU <ref>https://en.wikipedia.org/wiki/USB#Device_Firmware_Upgrade</ref>. | ||
This is used to access on-chip one time programmable memory | This is used to access the STM32MP's on-chip one time programmable memory, and is only supported in U-Boot. | ||
The OTP partition must be programmed without header and must have a fixed size of 1024 | The OTP partition must be programmed without a header and must have a fixed size of 1024 bytes = 256 words (32 bits), following the structure described in chapter [[#Data Structure]]. | ||
== Access operation == | === Access operation === | ||
For read operation, the host requests the OTP partition data and the platform replies with all the partition content (1024 bytes). | For read operation, the host requests the OTP partition data, and the platform replies with all the partition content (1024 bytes). | ||
For write operation, the host needs to send the full structure containing one or more modifications. Each field | For write operation, the host needs to send the full structure containing one or more modifications. Each field is analyzed by the platform. | ||
First the OTP values | First the OTP values are updated, then the OTP controls (such as lock) are updated. | ||
After any write operation, a read must be done to update the Host information. | After any write operation, a read must be done to update the Host information. | ||
== Data | === Data structure === | ||
The data structure for STM32MP15x Series is described in the table below. | The data structure for the STM32MP15x Series is described in the table below. | ||
Access can be RWS = Read / Write / Sticky | Access can be RWS = Read / Write / Sticky | ||
{| class=" | {| class="st-table" | ||
|- | |- | ||
! Word !! Field name !! Description !! RWS | ! Word !! Field name !! Description !! RWS | ||
Line 36: | Line 33: | ||
|- | |- | ||
| 1 || Configuration || | | 1 || Configuration || | ||
* Bit 8:7 TREAD[1:0]: set SAFMEM | * Bit 8:7 TREAD[1:0]: set SAFMEM reading current level (default = 0b00) | ||
* Bit 6:3 PRGWDTH[3:0] : SAFMEM | * Bit 6:3 PRGWDTH[3:0] : SAFMEM programming pulse width (default = 0b0001) | ||
* Bit 2:1 FRC[1:0]: SAFMEM CLOCK frequency range selection: | * Bit 2:1 FRC[1:0]: SAFMEM CLOCK frequency range selection: | ||
** 00: | ** 00: 10 MHz <= Freq <= 20 MHz | ||
** 01: | ** 01: 20 MHz <= Freq <= 30 MHz | ||
** 10: | ** 10: 30 MHz <= Freq <= 45 MHz | ||
** 11: | ** 11: 45 MHz <= Freq <= 67 MHz | ||
* Bit 0 PWRUP: SAFMEM | * Bit 0 PWRUP: SAFMEM power-up control | ||
** 0: SAFMEM is powered down. | ** 0: SAFMEM is powered down. | ||
** 1: SAFMEM is powered up | ** 1: SAFMEM is powered up | ||
Line 58: | Line 55: | ||
** 1: SAFMEM BIST1 is locked | ** 1: SAFMEM BIST1 is locked | ||
* Bits 5 PWRON: SAFMEM Power Status | * Bits 5 PWRON: SAFMEM Power Status | ||
** 0: SAFMEM is in | ** 0: SAFMEM is in power off | ||
** 1: SAFMEM is in | ** 1: SAFMEM is in power on | ||
** note: used to poll pwrok signal value | ** note: used to poll pwrok signal value | ||
* Bits 4 PROGFAIL: Last | * Bits 4 PROGFAIL: Last programming status | ||
** 0: SAFMEM last programming was successful | ** 0: SAFMEM last programming was successful | ||
** 1: SAFMEM last programming failed | ** 1: SAFMEM last programming failed | ||
* Bits 3 BUSY: SAFMEM | * Bits 3 BUSY: SAFMEM operation status | ||
** 0: SAFMEM is Idle | ** 0: SAFMEM is Idle | ||
** 1: SAFMEM operation is on going | ** 1: SAFMEM operation is on going | ||
** note: bit polling is used to determine operation completion | ** note: bit polling is used to determine operation completion | ||
* Bits 2 INVALID: OTP mode | * Bits 2 INVALID: OTP mode invalid | ||
** 0: OTP mode is not OTP-INVALID | ** 0: OTP mode is not OTP-INVALID | ||
** 1: OTP mode is OTP-INVALID | ** 1: OTP mode is OTP-INVALID | ||
* Bits 1 FULLDBG: OTP mode in | * Bits 1 FULLDBG: OTP mode in full debug | ||
** 0: OTP mode is OTP-OPEN1 | ** 0: OTP mode is OTP-OPEN1 | ||
** 1: OTP mode is OTP-OPEN2 | ** 1: OTP mode is OTP-OPEN2 | ||
* Bits 0 SECURE: OTP mode | * Bits 0 SECURE: OTP mode secured | ||
** 0: OTP mode is not OTP-SECURED | ** 0: OTP mode is not OTP-SECURED | ||
** 1: OTP mode is OTP-SECURED | ** 1: OTP mode is OTP-SECURED | ||
Line 80: | Line 77: | ||
|- | |- | ||
| 4 || General Lock conf || | | 4 || General Lock conf || | ||
* Bit4 GPLOCK: SAFMEM | * Bit4 GPLOCK: SAFMEM programming sticky lock | ||
** 0: SAFMEM | ** 0: SAFMEM programming allowed | ||
** 1: SAFMEM | ** 1: SAFMEM programming is disabled until the next system-reset | ||
* Bit 3 FENREG | * Bit 3 FENREG feature enable register sticky lock | ||
** 0: BSEC_FENABLE register is not | ** 0: BSEC_FENABLE register is not locked | ||
** 1: BSEC_FENABLE register is | ** 1: BSEC_FENABLE register is locked until the next system reset | ||
* Bit 2 DENREG | * Bit 2 DENREG debug enable register sticky lock | ||
** 0: BSEC_DENABLE register is not | ** 0: BSEC_DENABLE register is not locked | ||
** 1: BSEC_DENABLE register is | ** 1: BSEC_DENABLE register is locked until the next system reset | ||
* Bit 1 : Reserved, must be kept at reset value. | * Bit 1 : Reserved, must be kept at reset value. | ||
* Bit 0 OTP: upper OTP region access: | * Bit 0 OTP: upper OTP region access: | ||
** 0: not locked | ** 0: not locked | ||
** 1: Locked until the next | ** 1: Locked until the next system reset, when locked, the upper region OTP can not be read out from SAFMEM. | ||
|| RWS | || RWS | ||
|- | |- | ||
| 5 || Debug conf || | | 5 || Debug conf || | ||
* Bits 31:11 Reserved, must be kept at reset value. | * Bits 31:11 Reserved, must be kept at reset value. | ||
* Bit 10 DBGSWENABLE: Control | * Bit 10 DBGSWENABLE: Control self-hosted debug enable with signal dbgswenable | ||
** 0: memory-mapped accesses to all ETM registers are disabled and return | ** 0: memory-mapped accesses to all ETM registers are disabled and return error | ||
** 1: no effect on external debugger accesses | ** 1: no effect on external debugger accesses | ||
* Bit 9 CFGDISABLE: Write access to secure GIC registers disable with signal: cfgsdisable | * Bit 9 CFGDISABLE: Write access to secure GIC registers disable with signal: cfgsdisable | ||
Line 107: | Line 104: | ||
** CPDISABLE[1] applies to CPU1 | ** CPDISABLE[1] applies to CPU1 | ||
** 0: All CP15 registers can be accessed | ** 0: All CP15 registers can be accessed | ||
** 1: Disable write access to some | ** 1: Disable write access to some secure CP15 registers into Cortex-A7 corresponding CPU | ||
* Bit 6 SPNIDEN: Secure | * Bit 6 SPNIDEN: Secure privilege non-invasive debug enable with signal spiden | ||
** 0: Secure | ** 0: Secure privilege non-invasive debug disabled | ||
** 1: Secure | ** 1: Secure privilege non-invasive debug enabled | ||
* Bit 5 SPIDEN: Secure | * Bit 5 SPIDEN: Secure privilege invasive debug enable with signal spniden | ||
** 0: Secure | ** 0: Secure privilege invasive debug disabled | ||
** 1: Secure | ** 1: Secure privilege invasive debug enabled | ||
* Bit 4 HDPEN: Hardware | * Bit 4 HDPEN: Hardware debug port enable with signal hdpen | ||
** 0: Hardware | ** 0: Hardware debug port disabled | ||
** 1: Hardware | ** 1: Hardware debug port enabled | ||
* Bit 3 DEVICEEN: Controls the access to | * Bit 3 DEVICEEN: Controls the access to debug component via external debug port by signal deviceen | ||
** 0: Disabled | ** 0: Disabled | ||
** 1: Enabled | ** 1: Enabled | ||
* Bit 2 NIDEN: Non | * Bit 2 NIDEN: Non-invasive debug enable with signal niden | ||
** 0: Non | ** 0: Non-invasive debug disabled | ||
** 1: Non | ** 1: Non-invasive debug enabled | ||
* Bit 1 DBGEN: Debug enable with signal dbgen | * Bit 1 DBGEN: Debug enable with signal dbgen | ||
** 0: Disabled | ** 0: Disabled | ||
** 1: Enabled | ** 1: Enabled | ||
* Bit 0 DFTEN: DFT enable with signal dften | * Bit 0 DFTEN: DFT enable with signal dften | ||
** 0: DFT | ** 0: DFT disabled | ||
** 1: DFT | ** 1: DFT enabled | ||
|| RW | || RW | ||
|- | |- | ||
| 6 || | | 6 || Reserved || || | ||
|| | |||
|- | |- | ||
| 7 || | | 7 || Reserved || || | ||
|- | |- | ||
| 8 || Disturbed | | 8 || Disturbed status 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 status | ||
* ... | * ... | ||
* Bit 0 : OTP 0 status | * Bit 0 : OTP 0 status | ||
|| R | || R | ||
|- | |- | ||
| 9 || Disturbed | | 9 || Disturbed status 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 status | ||
* ... | * ... | ||
* Bit 0 : OTP 32 status | * Bit 0 : OTP 32 status | ||
|| R | || R | ||
|- | |- | ||
| 10 || Disturbed | | 10 || Disturbed status 3 || | ||
* Bit 31 : OTP 95 | * Bit 31 : OTP 95 status | ||
* ... | * ... | ||
* Bit 0 : OTP 64 status | * Bit 0 : OTP 64 status | ||
|| R | || R | ||
|- | |- | ||
| 11 || | | 11 || Reserved || || | ||
|- | |- | ||
| 12 || | | 12 || Reserved || || | ||
|- | |- | ||
| 13 || | | 13 || Reserved || || | ||
|- | |- | ||
| 14 || Error | | 14 || Error status 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 status | ||
* ... | * ... | ||
* Bit 0 : OTP 0 status | * Bit 0 : OTP 0 status | ||
|| R | || R | ||
|- | |- | ||
| 15 || Error | | 15 || Error status 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 status | ||
* ... | * ... | ||
* Bit 0 : OTP 32 status | * Bit 0 : OTP 32 status | ||
|| R | || R | ||
|- | |- | ||
| 16 || Error | | 16 || Error status 3 || | ||
* Bit 31 : OTP 95 | * Bit 31 : OTP 95 status | ||
* ... | * ... | ||
* Bit 0 : OTP 64 status | * Bit 0 : OTP 64 status | ||
|| R | || R | ||
|- | |- | ||
| 17 || | | 17 || Reserved || || | ||
|- | |- | ||
| 18 || | | 18 || Reserved || || | ||
|- | |- | ||
| 19 || | | 19 || Reserved || || | ||
|- | |- | ||
| 20 || Permanent | | 20 || Permanent lock 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 permanent lock | ||
* ... | * ... | ||
* Bit 0 : OTP 0 | * Bit 0 : OTP 0 permanent lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 21 || Permanent | | 21 || Permanent lock 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 permanent lock | ||
* ... | * ... | ||
* Bit 0 : OTP 32 | * Bit 0 : OTP 32 permanent lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 22 || Permanent | | 22 || Permanent lock 3 || | ||
* Bit 31 : OTP 95 Permanent | * Bit 31 : OTP 95 Permanent lock | ||
* ... | * ... | ||
* Bit 0 : OTP 64 | * Bit 0 : OTP 64 permanent lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 23 || | | 23 || Reserved || || | ||
|- | |- | ||
| 24 || | | 24 || Reserved || || | ||
|- | |- | ||
| 25 || | | 25 || Reserved || || | ||
|- | |- | ||
| 26 || Programming | | 26 || Programming lock 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 programming lock | ||
* ... | * ... | ||
* Bit 0 : OTP 0 | * Bit 0 : OTP 0 programming lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 27 || Programming | | 27 || Programming lock 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 programming lock | ||
* ... | * ... | ||
* Bit 0 : OTP 32 | * Bit 0 : OTP 32 programming lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 28 || Programming | | 28 || Programming lock 3 || | ||
* Bit 31 : OTP 95 | * Bit 31 : OTP 95 programming lock | ||
* ... | * ... | ||
* Bit 0 : OTP 64 | * Bit 0 : OTP 64 programming lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 29 || | | 29 || Reserved || || | ||
|- | |- | ||
| 30 || | | 30 || Reserved || || | ||
|- | |- | ||
| 31 || | | 31 || Reserved || || | ||
|- | |- | ||
| 32 || Shadow | | 32 || Shadow write lock 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 shadow write lock | ||
* ... | * ... | ||
* Bit 0 : OTP 0 | * Bit 0 : OTP 0 shadow write lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 33 || Shadow | | 33 || Shadow write lock 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 shadow write lock | ||
* ... | * ... | ||
* Bit 0 : OTP 32 | * Bit 0 : OTP 32 shadow write lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 34 || Shadow | | 34 || Shadow write lock 3 || | ||
* Bit 31 : OTP 95 | * Bit 31 : OTP 95 shadow write lock | ||
* ... | * ... | ||
* Bit 0 : OTP 64 | * Bit 0 : OTP 64 shadow write lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 35 || | | 35 || Reserved || || | ||
|- | |- | ||
| 36 || | | 36 || Reserved || || | ||
|- | |- | ||
| 37 || | | 37 || Reserved || || | ||
|- | |- | ||
| 38 || Shadow | | 38 || Shadow read lock 1 || | ||
* Bit 31 : OTP 31 | * Bit 31 : OTP 31 shadow read lock | ||
* ... | * ... | ||
* Bit 0 : OTP 0 | * Bit 0 : OTP 0 shadow read lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 39 || Shadow | | 39 || Shadow read lock 2 || | ||
* Bit 31 : OTP 63 | * Bit 31 : OTP 63 shadow read lock | ||
* ... | * ... | ||
* Bit 0 : OTP 32 | * Bit 0 : OTP 32 shadow read lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 40 || Shadow | | 40 || Shadow read lock 3 || | ||
* Bit 31 : OTP 95 | * Bit 31 : OTP 95 shadow read lock | ||
* ... | * ... | ||
* Bit 0 : OTP 64 | * Bit 0 : OTP 64 shadow read lock | ||
|| RWS | || RWS | ||
|- | |- | ||
| 41 || | | 41 || Reserved || || | ||
|- | |- | ||
| 42 || | | 42 || Reserved || || | ||
|- | |- | ||
| 43 || | | 43 || Reserved || || | ||
|- | |- | ||
| 44 || OTP 0 || Value of OTP 0 || RW | | 44 || OTP 0 || Value of OTP 0 || RW | ||
Line 300: | Line 284: | ||
| 139 || OTP95 || Value of OTP 95 || RW | | 139 || OTP95 || Value of OTP 95 || RW | ||
|- | |- | ||
| 140 || | | 140 || Reserved || || | ||
|- | |- | ||
| ... || | | ... || Reserved || || | ||
|- | |- | ||
| 251 || | | 251 || Reserved || || | ||
|- | |- | ||
| 252 || Configuration register || | | 252 || Configuration register || | ||
* Bit 7:4 ECC_USE[3:0]: | * Bit 7:4 ECC_USE[3:0]: | ||
** 0x0: No | ** 0x0: No | ||
** 0x1: SAFMEM use ECC for | ** 0x1: SAFMEM use ECC for upper OTP bits | ||
** others: Reserved | ** others: Reserved | ||
* Bit 3:0 SAFMEM_SIZE[3:0]: | * Bit 3:0 SAFMEM_SIZE[3:0]: | ||
** 0x2: | ** 0x2: 2 Kbytes | ||
** 0x4: | ** 0x4: 4 Kbytes | ||
** 0x8: | ** 0x8: 8 Kbytes | ||
** others: Reserved | ** others: Reserved | ||
|| R | || R | ||
|- | |- | ||
| 253 || IP version || | | 253 || IP version || | ||
* Bit 7:4 MAJREV[3:0]: IP | * Bit 7:4 MAJREV[3:0]: IP version major revision information | ||
* Bit 3:0 MINREV[3:0]: IP | * Bit 3:0 MINREV[3:0]: IP version minor revision information | ||
|| R | || R | ||
|- | |- | ||
Line 328: | Line 312: | ||
|} | |} | ||
= Reference list = | == Reference list == | ||
<references /> | <references /> | ||
<noinclude> | |||
[[Category:STM32CubeProgrammer]] | |||
{{PublicationRequestId | 12896 | 2019-08-01}} | |||
</noinclude> |
Latest revision as of 12:33, 27 January 2020
STM32CubeProgrammer can be used to read and update the OTP of the device which is seen as a partition on the device .
This page describes the format of the partition used by embedded programming service to allow OTP access by STM32CubeProgrammer (see AN5275: USB DFU/USART protocols used in STM32MP1 Series bootloaders for protocol details).
Refer to STM32CubeProgrammer article to know how to use the STM32CubeProgrammer that is the official STMicroelectronics tool for update OTP on STM32 platforms.
1. OTP partition[edit source]
The OTP partition is identified by the reserved Id 0xF2 and is exported as a specific alternate setting of the USB DFU [1].
This is used to access the STM32MP's on-chip one time programmable memory, and is only supported in U-Boot.
The OTP partition must be programmed without a header and must have a fixed size of 1024 bytes = 256 words (32 bits), following the structure described in chapter #Data Structure.
1.1. Access operation[edit source]
For read operation, the host requests the OTP partition data, and the platform replies with all the partition content (1024 bytes).
For write operation, the host needs to send the full structure containing one or more modifications. Each field is analyzed by the platform. First the OTP values are updated, then the OTP controls (such as lock) are updated.
After any write operation, a read must be done to update the Host information.
1.2. Data structure[edit source]
The data structure for the STM32MP15x Series is described in the table below.
Access can be RWS = Read / Write / Sticky
Word | Field name | Description | RWS |
---|---|---|---|
0 | Version | Version of this structure | R |
1 | Configuration |
|
RW |
2 | Reserved | ||
3 | Status |
|
R |
4 | General Lock conf |
|
RWS |
5 | Debug conf |
|
RW |
6 | Reserved | ||
7 | Reserved | ||
8 | Disturbed status 1 |
|
R |
9 | Disturbed status 2 |
|
R |
10 | Disturbed status 3 |
|
R |
11 | Reserved | ||
12 | Reserved | ||
13 | Reserved | ||
14 | Error status 1 |
|
R |
15 | Error status 2 |
|
R |
16 | Error status 3 |
|
R |
17 | Reserved | ||
18 | Reserved | ||
19 | Reserved | ||
20 | Permanent lock 1 |
|
RWS |
21 | Permanent lock 2 |
|
RWS |
22 | Permanent lock 3 |
|
RWS |
23 | Reserved | ||
24 | Reserved | ||
25 | Reserved | ||
26 | Programming lock 1 |
|
RWS |
27 | Programming lock 2 |
|
RWS |
28 | Programming lock 3 |
|
RWS |
29 | Reserved | ||
30 | Reserved | ||
31 | Reserved | ||
32 | Shadow write lock 1 |
|
RWS |
33 | Shadow write lock 2 |
|
RWS |
34 | Shadow write lock 3 |
|
RWS |
35 | Reserved | ||
36 | Reserved | ||
37 | Reserved | ||
38 | Shadow read lock 1 |
|
RWS |
39 | Shadow read lock 2 |
|
RWS |
40 | Shadow read lock 3 |
|
RWS |
41 | Reserved | ||
42 | Reserved | ||
43 | Reserved | ||
44 | OTP 0 | Value of OTP 0 | RW |
45 | OTP 1 | Value of OTP 1 | RW |
... | OTP ... | Value of OTP ... | RW |
139 | OTP95 | Value of OTP 95 | RW |
140 | Reserved | ||
... | Reserved | ||
251 | Reserved | ||
252 | Configuration register |
|
R |
253 | IP version |
|
R |
254 | IP ID | R | |
255 | IP_Magic_ID | R |
2. Reference list[edit source]