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'''SUMMARY '''<br> | '''SUMMARY '''<br> | ||
This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system. | This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system. | ||
== System overview== | == System overview== | ||
The STM32 MPU multiprocessor system allows to run independent | The STM32 MPU multiprocessor system allows to run independent firmwares on each CPU core. The below subsystems are involved in the management of the coexistence of the two CPU subsystems: | ||
* A | * A Arm<sup>®</sup> Cortex<sup>®</sup>-A acting as main processor and optimized to run the Linux<sup>®</sup> based OS. | ||
* A | * A Arm<sup>®</sup> Cortex<sup>®</sup>-M coprocessor which can run the RTOS optimized for microcontrollers or a bare-metal application. | ||
* [[STM32MP15_RAM_mapping#Memory_mapping| Internal memory regions]] | * [[STM32MP15_RAM_mapping#Memory_mapping| Internal memory regions]] with access granted for both the master and/or the slave processors: | ||
** To load and execute coprocessor firmware and define static common structures. | ** To load and execute coprocessor firmware and define static common structures. | ||
** To share buffers for inter processing communication through a messaging infrastructure. | ** To share buffers for inter processing communication through a messaging infrastructure. | ||
* [[IPCC internal peripheral| An | * [[IPCC internal peripheral| An inter-processor communication controller peripheral]] allowing a signaling system by a dedicated mailbox. | ||
* [[STM32MP15 peripherals overview | Internal peripheral resources]] that can be assigned to the master or the slave processor. | * [[STM32MP15 peripherals overview | Internal peripheral resources]] that can be assigned to the master or the slave processor. | ||
| Line 23: | Line 15: | ||
==Functional features and design== | ==Functional features and design== | ||
In order to manage the coprocessor system, a list of services is proposed relying on the open-source RemoteProc and RPMsg frameworks: | In order to manage the coprocessor system, a list of services is proposed relying on the open-source '''RemoteProc''' and '''RPMsg''' frameworks. | ||
These frameworks are introduced in chapters below with links to dedicated articles for further explanation. | |||
[[File:copro-sw-overview.png|link=]] | |||
===Load and control the Cortex-M firmware=== | |||
The Linux OS integrates the[[Linux remoteproc framework overview | RemoteProc]] framework that allows to load firmware and control remote processors. | |||
===Resources management (for shared peripheral, clocks, GPIOs...)=== | |||
The [[Resource_manager_for_coprocessing | resource manager]] proposes services to manage common resources and avoid any conflict. | |||
* '''Peripheral assignment request''': the mechanism used to ensure that a peripheral is reserved for a processor usage. The principle is that a firmware requests the peripheral before starting to use it, relying on the [[ETZPC_internal_peripheral| ETZPC]] table. | |||
:* On Cortex-A: At boot time, the ETZPC and Linux device tree are configured according to the [[TF-A_overview|TF-A]]<sup>®</sup> device tree (refer to [[How to assign an internal peripheral to a runtime context]] for details). | |||
:* On Cortex-M: the service is implemented by the '''Resource manager''' utilities. | |||
* '''Coprocessor resource configuration set''': services available in the main processor (Cortex-A running Linux) to configure the system resources needed to operate the peripheral on the coprocessor. The service is implemented by '''rproc_srm''' driver. | |||
===Inter processor communication=== | |||
Inter processor communication is based on '''RPMsg''' framework and '''Mailbox''' mechanisms. | |||
:*On Cortex-A: | |||
[[File:copro-sw-ipc-overview.png|link=]] | |||
*On Cortex-A: | |||
:* The [[Linux remoteproc framework overview | RemoteProc]] framework is in charge of enabling the IPC on Linux side, based on information available in the firmware [[Coprocessor_resource_table | resource table]]. | |||
:* The RPMsg service is implemented by the [[Linux RPMsg framework overview| RPMsg]] framework. | |||
:* The Mailbox service is implemented by the [[Linux Mailbox framework overview| stm32_ipcc mailbox ]] driver. | |||
*On Cortex-M: | |||
:* The RPMsg service is implemented by the [http://www.multicore-association.org/workgroup/oamp.php OpenAMP] library . | |||
:* The Mailbox service is implemented by the HAL_IPCC driver. | |||
[[ | <noinclude> | ||
[[Category:Coprocessor management Linux]] | |||
[[Category:Coprocessor management STM32Cube]] | |||
{{PublicationRequestId | 9717| 2018-11-28}} | |||
</noinclude> | |||
Latest revision as of 11:13, 12 September 2019
SUMMARY
This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system.
1. System overview[edit source]
The STM32 MPU multiprocessor system allows to run independent firmwares on each CPU core. The below subsystems are involved in the management of the coexistence of the two CPU subsystems:
- A Arm® Cortex®-A acting as main processor and optimized to run the Linux® based OS.
- A Arm® Cortex®-M coprocessor which can run the RTOS optimized for microcontrollers or a bare-metal application.
- Internal memory regions with access granted for both the master and/or the slave processors:
- To load and execute coprocessor firmware and define static common structures.
- To share buffers for inter processing communication through a messaging infrastructure.
- An inter-processor communication controller peripheral allowing a signaling system by a dedicated mailbox.
- Internal peripheral resources that can be assigned to the master or the slave processor.
2. Functional features and design[edit source]
In order to manage the coprocessor system, a list of services is proposed relying on the open-source RemoteProc and RPMsg frameworks. These frameworks are introduced in chapters below with links to dedicated articles for further explanation.
2.1. Load and control the Cortex-M firmware[edit source]
The Linux OS integrates the RemoteProc framework that allows to load firmware and control remote processors.
[edit source]
The resource manager proposes services to manage common resources and avoid any conflict.
- Peripheral assignment request: the mechanism used to ensure that a peripheral is reserved for a processor usage. The principle is that a firmware requests the peripheral before starting to use it, relying on the ETZPC table.
- On Cortex-A: At boot time, the ETZPC and Linux device tree are configured according to the TF-A® device tree (refer to How to assign an internal peripheral to a runtime context for details).
- On Cortex-M: the service is implemented by the Resource manager utilities.
- Coprocessor resource configuration set: services available in the main processor (Cortex-A running Linux) to configure the system resources needed to operate the peripheral on the coprocessor. The service is implemented by rproc_srm driver.
2.3. Inter processor communication[edit source]
Inter processor communication is based on RPMsg framework and Mailbox mechanisms.
- On Cortex-A:
- The RemoteProc framework is in charge of enabling the IPC on Linux side, based on information available in the firmware resource table.
- The RPMsg service is implemented by the RPMsg framework.
- The Mailbox service is implemented by the stm32_ipcc mailbox driver.
- On Cortex-M:
- The RPMsg service is implemented by the OpenAMP library .
- The Mailbox service is implemented by the HAL_IPCC driver.