STM32MP15 RNG internal peripheral

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STM32MP15x lines

1 Article purpose[edit source]

The purpose of this article is to:

briefly introduce the RNG peripheral and its main features
indicate the level of security supported by this hardware block
explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
explain how to configure the RNG peripheral.

2 Peripheral overview[edit source]

The RNG peripheral is used to provide 32-bit random numbers.

2.1 Features[edit source]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

2.2 Security support[edit source]

RNG1 is a secure peripheral (under ETZPC control).
RNG2 is a non-secure peripheral.

3 Peripheral usage and associated software[edit source]

3.1 Boot time[edit source]

RNG instances are not used as boot devices.

3.2 Runtime[edit source]

3.2.1 Overview[edit source]

RNG instances can be allocated to:

the Arm^® Cortex^®-A7 secure core to be controlled in OP-TEE with OP-TEE RNG driver

or

the Arm^® Cortex^®-A7 non-secure core to be controlled in Linux^® by the Linux hardware random framework

or

the Arm^® Cortex^®-M4 to be controlled in STM32Cube MPU Package by STM32Cube RNG driver

Chapter #Peripheral assignment exposes which instance can be assigned to which context.

3.2.2 Software frameworks[edit source]

Domain	Peripheral	Software components			Comment
Domain	Peripheral	OP-TEE	Linux	STM32Cube	Comment
Security	RNG	OP-TEE RNG driver	Linux hardware random framework	STM32Cube RNG driver

3.2.3 Peripheral configuration[edit source]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4 Peripheral assignment[edit source]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Security	RNG	RNG1	☐	☐		Assignment (single choice)
Security	RNG	RNG2			☐