STM32MP13 SRAM internal memory

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STM32MP13x lines

1. Article purpose[edit source]

The purpose of this article is to

briefly introduce the SRAM memory and its main features
indicate the level of security supported by this hardware block
explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
explain how to configure the SRAM memory.

2. Peripheral overview[edit source]

The SRAM internal memory is 32-Kbyte wide, split into three separate banks:

SRAM1 (16 Kbytes)
SRAM2 (8 Kbytes)
SRAM3 (8 Kbytes)

Those banks have individual security control (see security support below) and automatic clock gating (for power management optimization), but they are not supplied when the system goes to Standby low power mode, so their content is lost in that case.

2.1. Features[edit source]

Refer to STM32MP13 reference manuals for the complete features list, and to the software components, introduced below, to know which features are really implemented.

2.2. Security support[edit source]

Each SRAM1/SRAM2/SRAM3 bank is secure aware (under ETZPC control).

3. Peripheral usage and associated software[edit source]

3.1. Boot time[edit source]

The ROM code uses:

the SRAM1 and SRAM2 to store internal data
the SRAM3 to store the FSBL header

This mapping strategy aims to leave the whole SYSRAM internal memory free for FSBL binary loading then execution.

3.2. Runtime[edit source]

3.2.1. Overview[edit source]

Each SRAM bank can be allocated to:

the Arm^® Cortex^®-A7 secure for using in OP-TEE

or

the Arm^® Cortex^®-A7 non-secure for using in Linux^® with reserved memory, that is used by the dmaengine (for DMA buffers management)

The default assignement set in STMicroelectronics distribution is in line with the platform memory mapping, that can be adapted by the platform user.

3.2.2. Software frameworks[edit source]

Domain	Peripheral	Software components		Comment
Domain	Peripheral	OP-TEE	Linux	Comment
Core/RAM	SRAM	OP-TEE overview	Linux reserved memory

3.2.3. Peripheral configuration[edit source]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be done via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

3.2.4. Peripheral assignment[edit source]

Click on the right to expand the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Comment
Core/RAM	SRAM	SRAM1	☐	☐	Assignment (between A7 S and A7 NS)
		SRAM2	☐	☐	Assignment (between A7 S and A7 NS)
		SRAM3	☐	☐	Assignment (between A7 S and A7 NS)