STM32MP15 HASH internal peripheral

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STM32MP15x lines

1. Article purpose[edit source]

The purpose of this article is to:

briefly introduce the HASH peripheral and its main features
indicate the level of security supported by this hardware block
explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
explain, when necessary, how to configure the HASH peripheral.

2. Peripheral overview[edit source]

The HASH peripheral is used to compute a message digest.
Digest algorithms could be:

MD5^[1]
SHA^[2] (1, 224, 256)

The HASH peripheral is also able to give the HMAC^[3] used for authentication using the same algorithm support.

2.1. Features[edit source]

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2. Security support[edit source]

HASH1 is a secure peripheral (under ETZPC control)
HASH2 is a non secure peripheral .

3. Peripheral usage and associated software[edit source]

3.1. Boot time[edit source]

HASH1 instance is used as boot device to support binary authentication.
HASH2 is not used at boot time.

3.2. Runtime[edit source]

3.2.1. Overview[edit source]

HASH1 instance can be allocated to:

the Arm^® Cortex^®-A7 secure core to be controlled in OP-TEE by the OP-TEE HASH driver

or

the Arm^® Cortex^®-A7 non-secure core to be controlled in Linux^® by the Linux Crypto framework

HASH2 instance can be allocated to:

the Arm^® Cortex^®-M4 to be controlled in STM32Cube MPU Package by STM32Cube HASH driver

Chapter Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2. Software frameworks[edit source]

Domain	Peripheral	Software components			Comment
Domain	Peripheral	OP-TEE	Linux	STM32Cube	Comment
Security	HASH	OP-TEE HASH driver	Linux Crypto framework	STM32Cube HASH driver

3.2.3. Peripheral configuration[edit source]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4. Peripheral assignment[edit source]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Security	HASH	HASH1	☐	☐		Assignment (single choice)
Security	HASH	HASH2			☐

4. References[edit source]

[1] ttps://en.wikipedia.org/wiki/MD5

[2] ttps://en.wikipedia.org/wiki/Secure_Hash_Algorithms

[3] ttps://en.wikipedia.org/wiki/HMAC

[1]

[2]

[3]