How to adjust USBPHYC settings using USB Eye Diagram

1. General recommendations

At IC level, Eye Diagram is characterized with a specific reference resistor between USB_RREF and ground.

Verify first that USB_RREF resistor is correctly connected and has proper value and precision (3 kΩ 1%)

2. Eye Diagram

2.1. Common mode troubleshooting

Hardware root causes to investigate

• Mismatch between D+ and D- (in terms of length and/or parallelism)
• Check layout and add common mode filter (e.g. ECMF02-2AMX6)

Information

It is not possible to solve common mode issue with software.

2.2. Jitter troubleshooting

Hardware root causes to investigate

• Too much capacitance (component or PCB) on D+/D- lines
• USB Power/GND instability

Check decoupling / Check grounding

Software potential tuning

Only fine tuning available. High jitter has an HW root cause in most cases.

• USBPHYC_TUNEx.HSDRVRFRED

0: increase rising edge but add jitter (i.e. remove st,enable-hs-rftime-reduction;)

• USBPHYC_TUNEx.INCURREN/.INCURRINT

Reduce current increase with .INCURREN=0 or .INCURRINT=0 (i.e. remove st,current-boost-microamp= <n>;)

• USBPHYC_TUNEx.HSDRVCHKITRM

Reduce the increase of the main level (i.e. reduce value of st,trim-hs-current = <n>;)

2.3. Level attenuation or Signal-to-Noise troubleshooting

Hardware root causes to investigate

• too much serial resistance and capacitance (component or PCB) on D+/D- lines
• USB Power/GND instability

Check decoupling / Check grounding

Software potential tuning

• USBPHYC_TUNEx.HSDRVCHKITRM

Higher the value, higher will be the level of signal (i.e. increase value of st,trim-hs-current = <n>;).

But noise and ripple can appear

• USBPHYC_TUNEx.HSDRVCURINCR/.HSDRVDCLEV

Higher the value, higher will be the margin for the level (i.e. increase value of st,hs-dc-level = <n>;).

But jitter in the rising edge and noise can appear

2.4. Rising edge or Falling edge troubleshooting

Hardware root causes to investigate

• too much serial resistance and capacitance (component or PCB) on D+/D- lines
• Impedance mismatch : check characteristic impedance of lines, stubs…

Software potential tuning

• USBPHYC_TUNEx.HSDRVRFRED

0: improve rising edge (i.e. remove st,enable-hs-rftime-reduction;)

1: slow-down rising edge (i.e. add st,enable-hs-rftime-reduction;)

Potential impact on jitter

• USBPHYC_TUNEx.HSDRVCHKITRM

Depending on level, slope is increased/decreased (i.e. adjust value of st,trim-hs-current = <n>;)

• USBPHYC_TUNEx.HSDRVSLEW

0: normal rising edge (i.e. remove st,decrease-hs-slew-rate;)

1: reduce rising edge (i.e. add st,decrease-hs-slew-rate;)

Useful to reduce a hill shape ripple on top of rising/falling edge

• USBPHYC_TUNEx.HSDRVCURINCR/.HSDRVDCLEV

Improve slope speed (i.e. increase value of st,hs-dc-level = <n>;).

But jitter in the rising edge and noise can appear

2.5. Ripple troubleshooting

Hardware root causes to investigate

• Impedance mismatch : check characteristic impedance of lines, stubs…

Software potential tuning

• USBPHYC_TUNEx.HSDRVCHKZTRM[1:0]

00: Usually open the eye but can create some jitter and ripple (i.e. st,trim-hs-impedance = <0>;)

11: Close the eye but can reduce jitter and ripple (i.e. st,trim-hs-impedance = <3>;)

• USBPHYC_TUNEx.HSDRVSLEW

0: normal rising edge (i.e. remove st,decrease-hs-slew-rate;)

1: reduce rising edge (i.e. add st,decrease-hs-slew-rate;)

Useful to reduce a hill shape ripple on top of rising/falling edge

3. Link between Register values and Device Tree description

Only few bitfields should be adjusted in the scope of Eye Diagram tuning. It is recommended to keep other as described in default Device Tree examples. See also USBPHYC device tree bindings

Device Tree item	details	USBPHYC_TUNEx field
st,current-boost-microamp	<1000> current boosting of 1mA	.INCURREN=1/.INCURRINT=0
	<2000> current boosting of 2mA	.INCURREN=1/.INCURRINT=1
st,no-lsfs-fb-cap	disables the LS/FS feedback capacitor	.LFSCAPEN=1
st,decrease-hs-slew-rate	slows the HS driver slew rate by 10%	.HSDRVSLEW=1
st,hs-dc-level	<0> normal level	.HSDRVCURINCR=0/.HSDRVDCCUR=0
	<1> increases the HS driver DC level by 5 to 7mV	.HSDRVCURINCR=1/.HSDRVDCLEV=0
	<2> increases the HS driver DC level by 10 to 14mV	.HSDRVCURINCR=1/.HSDRVDCLEV=1
	<3> decreases the HS driver DC level by 5 to 7mV	.HSDRVDCCUR=1
st,enable-fs-rftime-tuning	enables the FS rise/fall tuning option	.FSDRVRFADJ=1
st,enable-hs-rftime-reduction	enables the HS rise/fall reduction feature	.HSDRVRFRED=1
st,trim-hs-current	controls HS driver current trimming for choke	.HSDRVCHKITRM=n [0:15]
st,trim-hs-impedance	controls HS driver impedance tuning for choke	.HSDRVCHKZTRM=n [0:3]
st,tune-squelch-level	adjusts the squelch DC threshold value	.SQLCHCTL=n [0:3]
st,enable-hs-rx-gain-eq	enables the HS Rx gain equalizer	.HDRXGNEQEN
st,tune-hs-rx-offset	adjusts the HS Rx offset	.HSRXOFF=n [0:3]
st,no-hs-ftime-ctrl	disables the HS fall time control of single ended signals during pre-emphasis	.HSFALLPREEM=1
st,no-lsfs-sc	disables the short circuit protection in LS/FS driver	.SHTCCTCTLPROT
st,enable-hs-tx-staggering	enables the basic staggering in HS Tx mode	.STAGSEL

Printed circuit board

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