OTP word
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Bit field (size)
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Name
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Description
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0
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31-7 (25 bits)
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reserved
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6 (1 bit)
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is closed
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- 0: device is in open state, authentication is optional.
- 1: device is in close state, authentication is mandatory.
Warning
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The 'is_closed' bit must never be programmed to 1 on product without secure boot option available: this is indicated in the security field of the chip part number.
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5-0 (6 bits)
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reserved
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1-2
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-
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-
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See the reference manual
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3
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31-30 (2 bits)
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HSE value
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- 0b00: HSE is autodetected
- 0b01: HSE is 24 MHz
- 0b10: HSE is 25 MHz
- 0b11: HSE is 26 MHz
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29-27 (3 bits)
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primary boot source
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- 0: No primary boot source is defined
- 1: FMC NAND
- 2: QSPI NOR
- 3: e•MMC™
- 4: SD card
- 5: QSPI NAND
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26-24 (3 bits)
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secondary boot source
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- 0: No primary boot source is defined
- 1: FMC NAND
- 2: QSPI NOR
- 3: e•MMC™
- 4: SD card
- 5: QSPI NAND
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23-16 (8 bits)
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boot source disable
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If different from zero each bit disables a boot source
- 0b00000001: disable FMC NAND boot source
- 0b00000010: disable QSPI NOR boot source
- 0b00000100: disable e•MMC™ boot source
- 0b00001000: disable SD boot source
- 0b00010000: disable UART boot source
- 0b00100000: disable USB boot source
- 0b01000000: disable QSPI NAND boot source
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15 (1 bit)
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data cache disabling
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- 0: data cache is used by the ROM code
- 1: data cache is not used by the ROM code
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14-7 (8 bits)
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UART instances disabling
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If different from zero then each bit disables an UART instance
STM32MP13x lines
- 0b00000001: reserved
- 0b00000010: reserved
- 0b00000100: disable USART3
- 0b00001000: disable UART4
- 0b00010000: disable UART5
- 0b00100000: disable UART6
- 0b01000000: disable UART7
- 0b10000000: disable USART8
- 0b11111111: all UART instances are enabled
STM32MP15x lines
- 0b00000001: reserved
- 0b00000010: disable USART2
- 0b00000100: disable USART3
- 0b00001000: disable UART4
- 0b00010000: disable UART5
- 0b00100000: disable UART6
- 0b01000000: disable UART7
- 0b10000000: disable USART8
- 0b11111111: all UART instances are enabled
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6 (1 bit)
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USB DP pullup disabling
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- 0: USB DP pull-up is set
- 1: USB DP pull-up is not set
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5 (1 bit)
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PLL disabling
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- 0: PLLs for CPU and AXI are enable on cold boot
- 1: PLLs for CPU and AXI are not enable on cold boot
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4-3 (2 bits)
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SD card memory interface
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- 0: SDMMC1 with default AFMux
- 1: SDMMC1 with non default AFmux defined in OTP
- 2: SDMMC2 with AFmux defined in OTP
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2-1 (2 bits)
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e•MMC™ memory interface
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- 0: SDMMC2 with default AFMux
- 1: SDMMC1 with AFmux defined in OTP
- 2: SDMMC2 with non default AFmux defined in OTP
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0 (1 bit)
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QSPI non default AFmux
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- 0: QSPI uses default AFMux
- 1: QSPI uses AFmux defined in OTP
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4
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31-0 (32 bits)
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monotonic counter
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This is an anti rollback monotonic counter : on closed devices, the ROM code checks that it is less or equal to the one stored in the loaded image header.
- 0b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 32
- 0b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: monotonic counter value is 31
- 0b...
- 0b00000000000000000000000000000001: monotonic counter value is 1
- 0b00000000000000000000000000000000: monotonic counter value is 0
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5-7
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31-28 (4 bits)
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AFmux configuration - port1[3:0]
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Bank id
- 0: unused
- 1: Bank A
- 2: Bank B
- 3: Bank C
- 4: Bank D
- 5: Bank E
- 6: Bank F
- 7: Bank G
- 8: Bank H
- 9: Bank I
- 10: Bank J
- 11: Bank K
- 12: Bank Z
- 13: not applicable
- 14: not applicable
- 0b1111: Invalid configuration
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27-24 (4 bits)
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AFmux configuration - pin1[3:0]
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Pin id
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23-20 (4 bits)
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AFmux configuration - afmux1[3:0]
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AFmux value
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19-16 (4 bits)
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AFmux configuration - mode1[3:0]
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Pin mode
- 0: AF; No Pull; Low Speed
- 1: AF; No Pull; Medium Speed
- 2: AF; No Pull; High Speed
- 3: AF; Pull Up; Low Speed
- 4: AF; Pull Up; Medium Speed
- 5: AF; Pull Up; High Speed
- 6: AF; Pull Down; Low Speed
- 7: AF; Pull Down; Medium Speed
- 8: AF; Pull Down; High Speed
- 9: GPIO Output High
- 10: GPIO Output Low
- 11: GPIO Input
- 12: GPIO open drain; No pull
- 13: GPIO open drain; Pull Up
- 14: GPIO open drain; Pull Down
- 15: GPIO analog mode
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15-12 (4 bits)
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AFmux configuration - port0[3:0]
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Bank id
- 0: unused
- 1: Bank A
- 2: Bank B
- 3: Bank C
- 4: Bank D
- 5: Bank E
- 6: Bank F
- 7: Bank G
- 8: Bank H
- 9: Bank I
- 10: Bank J
- 11: Bank K
- 12: Bank Z
- 13: not applicable
- 14: not applicable
- 0b1111: Invalid configuration
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11-8 (4 bits)
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AFmux configuration - pin0[3:0]
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Pin id
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7-4 (4 bits)
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AFmux configuration - afmux0[3:0]
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AFmux value
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3-0 (4 bits)
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AFmux configuration - mode0[3:0]
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Pin mode
- 0: AF; No Pull; Low Speed
- 1: AF; No Pull; Medium Speed
- 2: AF; No Pull; High Speed
- 3: AF; Pull Up; Low Speed
- 4: AF; Pull Up; Medium Speed
- 5: AF; Pull Up; High Speed
- 6: AF; Pull Down; Low Speed
- 7: AF; Pull Down; Medium Speed
- 8: AF; Pull Down; High Speed
- 9: GPIO Output High
- 10: GPIO Output Low
- 11: GPIO Input
- 12: GPIO open drain; No pull
- 13: GPIO open drain; Pull Up
- 14: GPIO open drain; Pull Down
- 15: GPIO analog mode
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8 STM32MP13x lines
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31-0 (32 bits)
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reserved
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8 STM32MP15x lines
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31-10 (22 bits)
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reserved
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9 (1 bit)
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SSP success
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- 0: SSP is either not started or not finished
- 1: SSP is finished
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8 (1 bit)
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SSP request
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- 0: SSP has never been requested
- 1: SSP has been requested
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7-0 (8 bits)
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reserved
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9
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31 (1 bit)
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nand param stored in otp
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FMC and serial NAND parameters storage flag
- 0b0: NAND parameters are not stored here in OTP and are available via an ‘ONFI’ compliant get parameter command
- 0b1: NAND parameters are stored here in OTP
Notes:
- serial NAND parameters must always be stored in OTP.
- on STM32MP13x lines , there are two NAND parameters banks. The value of nand_config_distribution determines the bank to be used.
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30-29 (2 bits)
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nand page size[1:0]
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FMC or serial NAND page size
- 0: page size is 2 Kbytes
- 1: page size is 4 Kbytes
- 2: page size is 8 Kbytes
- 3: reserved
Note: on STM32MP13x lines , this parameter is part of NAND parameters bank1.
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28-27 (2 bits)
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nand block size[1:0]
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FMC or serial NAND block size
- 0: block size is 64 pages
- 1: block size is 128 pages
- 2: block size is 256 pages
- 3: reserved
Note: on STM32MP13x lines , this parameter is part of NAND parameters bank1.
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26-19 (8 bits)
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nand block nb[7:0]
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FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
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18 (1 bit)
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fmc nand width
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FMC NAND width
- 0: FMC NAND is 8 bits
- 1: FMC NAND is 16 bits
Note: on STM32MP13x lines , this parameter is part of NAND parameters bank1.
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17-15 (3 bits)
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fmc ecc bit nb[2:0]
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FMC NAND number of ECC bits
- 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’
- 1: 1 bit ECC per 512 bytes, Hamming code
- 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
- 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
- 4: on-die ECC
Note: on STM32MP13x lines , this parameter is part of NAND parameters bank1.
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14 (1 bit)
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spinand needs plane select
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Serial NAND needs plane select
- 0: serial NAND plane select not needed
- 1: serial NAND plane select needed
Note: on STM32MP13x lines , this parameter is part of NAND parameters bank1.
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13-8 (6 bits)
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reserved
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7 (1 bit)
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STM32MP13x lines
FSBL decryption priority
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- 0: use CRYP to priories speed
- 1: use SAES to priories security
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STM32MP15x lines
reserved
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6 (1 bit)
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STM32MP13x lines
SSP success
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- 0: SSP is either not started or not finished
- 1: SSP is finished
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STM32MP15x lines
reserved
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5 (1 bit)
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STM32MP13x lines
SSP request
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- 0: SSP has never been requested
- 1: SSP has been requested
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STM32MP15x lines
reserved
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4 (1 bit)
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STM32MP13x lines
eMMC 128KB boot partition support
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- 0: BootROM does not support eMMC with 128KBytes boot partition
- 1: BootROM supports eMMC with 128KBytes boot partition
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STM32MP15x lines
reserved
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3 (1 bit)
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disable ddr power optim
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Disable DDR PLL switch off sequence
- 0: DDR DLL switch off sequence enabled
- 1: DDR DLL switch off sequence disabled
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2 (1 bit)
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disable HSE bypass detection
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- 0: HSE bypass detection enabled
- 1: HSE bypass detection disabled
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1 (1 bit)
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disable HSE frequency autodetection
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- 0: HSE frequency autodetection enabled
- 1: HSE frequency autodetection disabled
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0 (1 bit)
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disable ROM code traces
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- 0: ROM code traces enabled
- 1: ROM code traces disabled
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10 STM32MP13x lines only.
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31-18 (14 bits)
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reserved
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17-16 (2 bits)
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nand page size[1:0]
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NAND parameters bank2 : FMC or serial NAND page size
- 0: page size is 2 Kbytes
- 1: page size is 4 Kbytes
- 2: page size is 8 Kbytes
- 3: reserved
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15-14 (2 bits)
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nand block size[1:0]
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NAND parameters bank2 : FMC or serial NAND block size
- 0: block size is 64 pages
- 1: block size is 128 pages
- 2: block size is 256 pages
- 3: reserved
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13-6 (8 bits)
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nand block nb[7:0]
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NAND parameters bank2 : FMC or serial NAND number of blocks in unit of 256 blocks (nb blocks = N * 256)
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5 (1 bit)
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fmc nand width
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NAND parameters bank2 : FMC NAND width
- 0: FMC NAND is 8 bits
- 1: FMC NAND is 16 bits
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4-2 (3 bits)
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fmc ecc bit nb[2:0]
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NAND parameters bank2 : FMC NAND number of ECC bits
- 0: no setting. In case of ONFI NAND, this means ‘use value defined in parameter table’
- 1: 1 bit ECC per 512 bytes, Hamming code
- 2: 4 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
- 3: 8 bits ECC per 512 bytes of data, BCH (Bose, Chaudhuri and Hocquenghem) code
- 4: on-die ECC
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1 (1 bit)
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spinand needs plane select
|
NAND parameters bank2 : serial NAND needs plane select
- 0: serial NAND plane select not needed
- 1: serial NAND plane select needed
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0 (1 bit)
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NAND configuration distribution
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Distribution of NAND parameters bank1 and bank2.
- 0: FMC NAND configuration in bank2 / serial NAND configuration in bank1
- 1: FMC NAND configuration in bank1 / serial NAND configuration in bank2
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11-21
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-
|
-
|
See the reference manual
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22 STM32MP13x lines only.
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31-8 (24 bits)
|
reserved
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7-0 (8 bits)
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signing key id monotonic counter
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This is an anti rollback monotonic counter used by the ROM to checks that it is less or equal to the active signing key id stored in the loaded image header.
- 0b1xxxxxxx: monotonic counter value is 8
- 0b01xxxxxx: monotonic counter value is 7
- 0b...
- 0b00000001: monotonic counter value is 1
- 0b00000000: monotonic counter value is 0
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23
|
-
|
-
|
See the reference manual
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24
|
31-0 (32 bits)
|
PKH[31:0]
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The Public Key Hash (PKH) is the SHA256 hash of ECDSA public key used for the Secure boot
|
25
|
31-0 (32 bits)
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PKH[63:32]
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26
|
31-0 (32 bits)
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PKH[95:64]
|
27
|
31-0 (32 bits)
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PKH[128:96]
|
28
|
31-0 (32 bits)
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PKH[159:128]
|
29
|
31-0 (32 bits)
|
PKH[191:160]
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30
|
31-0 (32 bits)
|
PKH[223:192]
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31
|
31-0 (32 bits)
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PKH[255:224]
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32-55
|
-
|
-
|
See the reference manual
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56
|
31-30 (2 bits)
|
reserved
|
|
29-15 (15 bits)
|
rma relock passwd
|
Password required for RMA relock request
|
14-0 (15 bits)
|
rma unlock passwd
|
Password required for RMA unlock request
|
57
|
31-0
|
mac[31:0]
|
ETH MAC address for STMicroelectronics boards
|
58
|
15-0
|
mac[47:32]
|
59-95
|
-
|
-
|
See the reference manual
|