1. Article purpose[edit source]
The purpose of this article is to explain STM32MP1 Series DMA topology and the associated configurations recommended by ST.
2. DMA specificities per STM32 MPU devices[edit source]
2.1. STM32MP13x lines
[edit source]
STM32MP13 owns 4 DMA instances:
- 1 MDMA internal peripheral dedicated to transfers between some internal peripherals and external memories (DDR), and between internal and external memories.
- 3 DMA internal peripheral (DMA1/DMA2/DMA3) dedicated to transfers between internal peripherals and internal SRAM. DMA1/DMA2 instances are coupled with DMAMUX1, DMA3 is coupled with DMAMUX2 : DMAMUX internal peripheral is in charge of routing internal peripheral requests to DMA channels.
2.2. STM32MP15x lines
[edit source]
STM32MP15 owns 3 DMA instances:
- 1 MDMA internal peripheral dedicated to transfers between some internal peripherals and external memories (DDR), and between internal and external memories.
- 2 DMA internal peripheral (DMA1/DMA2) dedicated to transfers between internal peripherals and internal SRAM. These 2 DMA instances are coupled with a DMAMUX internal peripheral in charge of routing internal peripheral requests to DMA channels.
3. DMA configurations[edit source]
The following figures show the different DMA configurations available on STM32MP1 and the associated requests and data connections. Legend below illustrates request lines and data path.
![DMA legend.png](/stm32mpu-ecosystem-v4/nsfr_img_auth.php/thumb/a/a9/DMA_legend.png/200px-DMA_legend.png)
- Internal peripherals - internal SRAM with DMA transfer
![DMA transfer.png](/stm32mpu-ecosystem-v4/nsfr_img_auth.php/thumb/3/33/DMA_transfer.png/700px-DMA_transfer.png)
- In this configuration, the data flow is:
- Internal peripherals - DDR with MDMA transfer
![MDMA transfer.png](/stm32mpu-ecosystem-v4/nsfr_img_auth.php/thumb/9/9a/MDMA_transfer.png/700px-MDMA_transfer.png)
- In this configuration, the data flow is:
![DMA MDMA transfer.png](/stm32mpu-ecosystem-v4/nsfr_img_auth.php/thumb/d/d0/DMA_MDMA_transfer.png/700px-DMA_MDMA_transfer.png)
- In this configuration, the data flow is:
- peripheral to memory direction: data are transferred from peripheral to temporary internal SRAM buffer by DMA then from temporary internal SRAM buffer to DDR buffer by MDMA.
- memory to peripheral direction: data are transferred from DDR buffer to temporary internal SRAM buffer by MDMA, then from temporary internal SRAM buffer to peripheral by DMA.
For more information about the DMA controllers above and,to know the DMA configuration that should be used with each internal peripheral, refer to reference manuals corresponding to the used STM32 MPU .
4. STMicroelectronics recommendations[edit source]
4.1. For Arm® Cortex®-M4 execution context[edit source]
Arm® Cortex®-M4 accesses by default internal SRAM for code and data.
In this context, DMA transfers will operate only between peripheral and internal SRAM.
That's why ST recommends to dedicate one DMA internal peripheral to Arm® Cortex®-M4.
4.2. For Arm® Cortex®-A7 secure execution context[edit source]
Arm® Cortex®-A7 secure firmware is located in SYSRAM (both code and data). As the internal peripherals and the SYSRAM associated to the Arm® Cortex®-A7 secure context are also secure, the MDMA must be used to support transfers between them because it is secure aware.
4.3. Arm® Cortex®-A7 non-secure execution context[edit source]
Arm® Cortex®-A7 non-secure firmware is mainly located in external memory (DDR). In consequence, DMA transfers will operate between peripherals and DDR. But as the different internal peripherals do not have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described in DMA configurations. To ease the selection, the following table sums up possible choices for each peripheral and highlight the recommended configuration. Note that this configuration is set by default in device tree (dtsi).
Peripheral | no DMA mode | DMA mode | MDMA mode | DMA-MDMA chaining mode | Default mode |
---|---|---|---|---|---|
U(S)ART | ![]() |
![]() |
![]() |
![]() |
no DMA mode |
ADC | ![]() |
![]() |
![]() |
![]() |
DMA-MDMA chaining mode |
SPI | ![]() |
![]() |
![]() |
![]() |
DMA or MDMA mode depending on instance |
SPDIFRx | ![]() |
![]() |
![]() |
![]() |
DMA mode |
SAI | ![]() |
![]() |
![]() |
![]() |
DMA mode |
I2C | ![]() |
![]() |
![]() |
![]() |
DMA or MDMA mode depending on instance |
Timer | ![]() |
![]() |
![]() |
![]() |
DMA-MDMA chaining mode |
DFSDM | ![]() |
![]() |
![]() |
![]() |
DMA mode |
I2S | ![]() |
![]() |
![]() |
![]() |
DMA mode |
DCMI | ![]() |
![]() |
![]() |
![]() |
DMA-MDMA chaining mode |
FMC | ![]() |
![]() |
![]() |
![]() |
MDMA mode |
QUADSPI | ![]() |
![]() |
![]() |
![]() |
MDMA mode |
HASH | ![]() |
![]() |
![]() |
![]() |
MDMA mode |
CRYP | ![]() |
![]() |
![]() |
![]() |
MDMA mode |
5. STMicroelectronics reference boards default configuration[edit source]
5.1. STM32MP135x-DK Discovery kit
DMA configuration[edit source]
The following table provides the list of the peripherals for which DMA is configured. Associated configurations are also described
Peripheral | Request line | DMA mode |
---|---|---|
ADC1 | rx | DMA-MDMA chaining mode |
ADC2 | rx | DMA-MDMA chaining mode |
CRYP1 | in | MDMA mode |
out | ||
HASH1 | in | MDMA mode |
I2S2 | rx | DMA mode |
tx | ||
SAI2 | a - tx | DMA mode |
b - rx | ||
USART2 | rx | DMA mode |
tx |
5.2. STM32MP157x-EV1 Evaluation board
DMA configuration[edit source]
The following table provides the list of the peripherals for which DMA is configured. Associated configurations are also described.
Peripheral | Request line | DMA mode |
---|---|---|
CRYP1 | in | MDMA mode |
out | ||
DCMI | tx | DMA-MDMA chaining mode |
DFSDM | channel 0 - rx | DMA mode |
channel 1 - rx | ||
channel 2 - rx | ||
channel 3 - rx | ||
HASH1 | in | MDMA mode |
I2S2 | rx | DMA mode |
tx | ||
SAI2 | a - tx | DMA mode |
b - rx | ||
USART2 | rx | DMA mode |
tx |