1. Article purpose[edit source]
The purpose of this article is to provide information on the Arm® CoreSight™ hardware subsystem.
It explains what are the principle peripherals of this subsystem.
2. Peripheral overview[edit source]
Arm® CoreSight™ products include
- a wide range of trace macrocells for Arm® processors,
To enable the debug and trace of the most complex, multi-core SoCs, Arm® CoreSight™ products include
- a system and software instrumentation,
- and a comprehensive set of IP blocks.
Arm® has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight™ infrastructure.
2.1. Components description[edit source]
The debug features are based on Arm® CoreSight™ components
Arm® CoreSight™ components | STM32MP13x lines ![]() |
STM32MP15x lines ![]() |
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SWJ-DP: JTAG/Serial-wire debug port | ![]() |
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AXI-AP: AXI access port | ![]() |
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AHB-AP: AHB access port | ![]() |
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APB-AP: APB access port | ![]() |
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ITM: Instrumentation Trace Macrocell | ![]() |
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DWT: Data Watchpoint and Trace | ![]() |
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ETM: Embedded Trace Macrocell | ![]() |
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ETF: Embedded Trace FIFO | ![]() |
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TPIU: Trace Port Interface Unit | ![]() |
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SWO: Serial Wire Output | ![]() |
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CTI: Cross Trigger Interface | ![]() |
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CTM: Cross Trigger Matrix | ![]() |
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TSGEN: Timestamp Generator | ![]() |
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STM: System Trace Macrocell | ![]() |
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More information about these components can be found in the Arm® website [1]
2.2. Features[edit source]
Refer to the Debug support (DBG) chapter of
- STM32MP13 reference manuals for STM32MP13x lines
- STM32MP15 reference manuals for STM32MP15x lines
for the complete list of features, and to the software components, introduced below, to see which features are really implemented.
3. References[edit source]