STM32MP13 ecosystem errata sheet

Applicable for

STM32MP13x lines

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The STM32MP13xx device errata sheet lists the different device limitations and explains the corresponding workarounds (software and/or hardware) if any.

The objective of this article is to explain which of the workarounds described in this errata sheet are implemented in STM32MP1-ecosystem-v4.1.0 release.

The section column provides the id of the errata in the errata sheet document. Here is the legend used i "Rev.Y" of the table below. It refers to the availability and status of a given errata workaround for the described erratum:

• A = workaround available
• P = partial workaround available
• N = no workaround available

Here is the legend used in the columns "OpenSTLinux" and "CubeMP1" of the table below. It refers to the availability of a workaround for a given STM32MP13 ecosystem release:

• U = workaround to implement by User
• I = workaround Implemented
• NA= Errata Not Applicable in ST SW release

Wave your mouse over a status in the table to display the corresponding legend.

1. Workarounds to implement by customer

Function	Section	Limitation	Rev.Y			Comment
Arm® Cortex®-A7 core	2.1.1	Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set	A	U	NA	STM32MPU Embedded Software distribution does not activate Arm® Cortex®-A7 Hypervisor mode and hence the Virtual Memory second stage of translation. The customer should implement the workaround if the Hypervisor mode is used in his/her product.
DMAMUX	2.3.4	Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event	A	NA	U	STM32MPU Embedded Software distribution: Not applicable to since DMA Synchronous mode is not used. STM32CubeMP1_Package: The customer should provide the right DMAMUX signal polarity configuration when calling the HAL_DMAEx_ConfigMuxSync() function provided in STM32CubeMP1_Package Src/stm32mp1xx_hal_dma_ex.c .
FMC	2.4.1	NOR Flash memory/PSRAM incorrect bus turnaround timing	A	U		STM32MPU Embedded Software distribution: Delays to applied by customer device tree.
ADC	2.6.8	ADC_AWDy_OUT reset by non-guarded channels	A	U	U	STM32MPU Embedded Software distribution: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the device tree STM32CubeMP1_Package: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the application.
LPTIM	2.9.1	Device may remain stuck in LPTIM interrupt when entering Stop mode	A	NA	U	STM32MPU Embedded Software distribution: The LPTIM interrupt is not used. STM32CubeMP1_Package: The customer should implement this workaround in MspDeinit().

2. Errata workarounds implemented in STM32MP13 ecosystem releases

Function	Section	Limitation	Rev.Y			Comment
Arm® Cortex®-A7 core	2.1.2	Cache maintenance by set/way operations can execute out of order	A	I	I	STM32MPU Embedded Software distribution: Implementation accepted by the community since Linux® kernel v5.3 in arch/arm/Kconfig (refer to ARM_ERRATA_814220).
System	2.2.2	Incorrect reset of glitch-free kernel clock switch	P	I		STM32MPU Embedded Software distribution: By default, STPMIC1 performs a VDDCORE reset on NRST activation.
QUADSPI	2.5.1	Memory-mapped read of last memory byte fails	P	I
DTS	2.7.1	DTS incorrect operation with LSE as reference clock and PCLK enabled	P	I
LPTIM	2.9.2	MCU may remain stuck in LPTIM interrupt when clearing event flag	P	NA	I
I2C	2.11.1	Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period	P	I	I	STM32MPU Embedded Software distribution: Workaround implemented in device tree with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz.
SPI	2.13.1	Master data transfer stall at system clock much faster than SCK	A	I	I	STM32MPU Embedded Software distribution: SPI is disabled after each EOT STM32CubeMP1_Package: SPI is disabled after each EOT.
	2.13.3	TXP interrupt occurring while SPI disabled	A	I	I	STM32MPU Embedded Software distribution: all interrupts are disabled before the SPI is disabled.
ETH	2.16.6	ARP offload function not effective	A	I

3. Errata workarounds not applicable in STM32MP13 ecosystem releases

Function	Section	Limitation	Rev.Y			Comment
DMAMUX	2.3.1	SOFx not asserted when writing into DMAMUX_CFR register	N	NA	N	STM32MPU Embedded Software distribution: DMA Synchronous mode is not used.
	2.3.4	Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event	A	NA	U	STM32MPU Embedded Software distribution: DMA Synchronous mode is not used.
FMC	2.4.2	Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode	A	NA		STM32MPU Embedded Software distribution: CLKDIV can't be changed on-the-fly.
	2.4.3	NAND Flash memory IREF/IFEF flags wrongly asserted just after enabling in FMC_IER	A	NA		STM32MPU Embedded Software distribution: IREF/IFEF flags are not used.
	2.4.4	Command sequencer accesses NAND Flash memory device while PBKEN bit is cleared in FMC_PCR	A	NA		STM32MPU Embedded Software distribution: PBKEN bit is set at probe time and never cleared on the flag.
	2.4.5	NAND Flash memory IREF flag wrongly asserted after reset	A	NA
ADC	2.6.1	Injected queue of context is not available if JQM = 0	N	NA	N	STM32MPU Embedded Software distribution: Injected conversion not implemented.
	2.6.2	Sampling time shortened in JAUTO auto delayed mode	A	NA		STM32MPU Embedded Software distribution: Injected conversion not implemented.
	2.6.5	New context conversion initiated without waiting for trigger when writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0	A	NA		STM32MPU Embedded Software distribution: JQDIS = 1.
	2.6.6	Two consecutive context conversions fail when writing new context in ADC_JSQR just after previous context completion with JQDIS = 0 and JQM = 0	A	NA		STM32MPU Embedded Software distribution: JQDIS = 1.
	2.6.7	Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode	A	NA		STM32MPU Embedded Software distribution: Dual mode is not implemented.
	2.6.9	Injected data stored in the wrong ADC_JDRx registers	A	NA		STM32MPU Embedded Software distribution: Injected conversion not implemented.
	2.6.10	ADC slave data may be shifted in Dual regular simultaneous mode	A	NA		STM32MPU Embedded Software distribution: Dual mode is not implemented.
LPTIM	2.9.1	Device may remain stuck in LPTIM interrupt when entering Stop mode	A	NA	U	STM32MPU Embedded Software distribution: LPTIM interrupt is not used
	2.9.2	MCU may remain stuck in LPTIM interrupt when clearing event flag	P	NA	I	STM32MPU Embedded Software distribution: LPTIM interrupt is not used
RTC and TAMP	2.10.2	Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1	A	NA		STM32MPU Embedded Software distribution: Binary mode is not used
USART	2.12.1	Anticipated end-of-transmission signaling in SPI slave mode	A	NA		STM32MPU Embedded Software distribution: SPI slave mode is not implemented
SPI	2.13.2	Corrupted CRC return at non-zero UDRDET setting	P	NA		CRC is not supported in OpenSTLinux distribution.	STM32MPU Embedded Software distribution: CRC is not supported
	2.13.4	Possible corruption of last-received data depending on CRCSIZE setting	A	NA		STM32MPU Embedded Software distribution: CRC is not supported

4. Draft, to be deleted when article will be completed

Previous ecosystem releases [Expand/Collapse]

Previous ecosystem releases [Expand/Collapse]

Function	Section	Limitation	Status for STM32MP13xx Rev.B	Status for STM32MP13xx Rev.Z	Status for ecosystem release v4.1.0	Comment about the workaround implemented in STM32MP13 ecosystem
Arm® Cortex®-A7 core	2.1.1	Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set	A	A	N	Workaround not implemented: STM32MPU Embedded Software distribution does not activate Arm® Cortex®-A7 Hypervisor mode and hence the Virtual Memory second stage of translation. It is customer responsibility to implement the workaround if the Hypervisor mode is used in his/her product.
	2.1.2	Cache maintenance by set/way operations can execute out of order	A	A	I	Implementation accepted by the community since Linux® kernel v5.3 in arch/arm/Kconfig (refer to ARM_ERRATA_814220).
	2.1.3	PMU events 0x07, 0x0C, and 0x0E do not increment correctly	A	N	TBC
	2.1.4	PMU event counter 0x14 does not increment correctly	A	A	N	No impact on the system. Minor impact on performance measurement. No workaround provided by Arm for Linux kernel PMU driver.
	2.1.5	Exception mask bits are cleared when an exception is taken in Hyp mode	A	N	TBC
System	2.2.1	TPIU fails to output sync after the pattern generator is disabled in Normal mode	A	A	N	No workaround implemented. No impact on the system since this issue occurs only on the trace port.
	2.2.2	Incorrect reset of glitch-free kernel clock switch	A	P	TBC
	2.2.3	SAES, RNG, PKA stuck after first stage bootloader (FSBL) decryption	P	A	TBC
DMAMUX	2.3.1	SOFx not asserted when writing into DMAMUX_CFR register	A	N	TBC
	2.3.2	OFx not asserted for trigger event coinciding with last DMAMUX request	A	N	TBC	.
	2.3.3	OFx not asserted when writing into DMAMUX_RGCFR register	A	N	TBC
	2.3.4	Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event	A	A	P	Not applicable to OpenSTLinux distribution since DMA Synchronous mode is not used. It is customer responsibility to provide the right DMAMUX signal polarity configuration when calling the HAL_DMAEx_ConfigMuxSync() function provided in STM32CubeMP1 Package Src/stm32mp1xx_hal_dma_ex.c .
FMC	2.4.1	NOR Flash memory/PSRAM incorrect bus turnaround timing	A	A	TBC
	2.4.2	Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode	A	A	TBC
	2.4.3	NAND Flash memory IREF/IFEF flags wrongly asserted just after enabling in FMC_IER	A	A	TBC
	2.4.4	Command sequencer accesses NAND Flash memory device while PBKEN bit is cleared in FMC_PCR	A	A	TBC
	2.4.5	NAND Flash memory IREF flag wrongly asserted after reset	A	A	TBC
	2.4.6	NAND ECC corrupted due to insufficient ECCEN low period in between sectors	A	A	TBC
QUADSPI	2.5.1	Memory-mapped read of last memory byte fails	P	P	A	Implemented in OpenSTLinux distribution drivers/spi/spi-stm32-qspi.c
ADC	2.6.1	Injected queue of context is not available if JQM = 0	P	N	TBC
	2.6.2	Sampling time shortened in JAUTO auto delayed mode	P	A	TBC
	2.6.3	Load multiple not supported by ADC interface	P	A	TBC
	2.6.4	Overrun flag might not be set when converted data have not been read before new data are written	P	A	TBC
	2.6.5	New context conversion initiated without waiting for trigger when writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0	A	A		Not applicable to Linux stm32-adc driver , since JQDIS = 1.
	2.6.6	Two consecutive context conversions fail when writing new context in ADC_JSQR just after previous context completion with JQDIS = 0 and JQM = 0	P	A		Not applicable to Linux stm32-adc driver , since JQDIS = 1.
	2.6.7	Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode	A	A		Not applicable to Linux stm32-adc driver , since Dual mode is not used.
	2.6.8	ADC_AWDy_OUT reset by non-guarded channels	A	A	TBC
	2.6.9	Injected data stored in the wrong ADC_JDRx registers	A	A	TBC
	2.6.10	ADC slave data may be shifted in Dual regular simultaneous mode	A	A	TBC
DTS	2.7.1	DTS incorrect operation with LSE as reference clock and PCLK enabled	A	A	TBC
TIM	2.8.1	One-pulse mode trigger not detected in master-slave reset + trigger configuration	P	P	N	This workaround is proposed only as a recommendation.
	2.8.2	Consecutive compare event missed in specific conditions	P	N	TBC	This workaround is proposed only as a recommendation.
	2.8.3	Output compare clear not working with external counter reset	P	P	TBC
LPTIM	2.9.1	Device may remain stuck in LPTIM interrupt when entering Stop mode	A	A	N	The LPTIM interrupt is not used in OpenSTLinux distribution. This workaround is not implemented in STM32CubeMP1 Package. It is customer responsibility to implement it in MspDeinit().
	2.9.2	MCU may remain stuck in LPTIM interrupt when clearing event flag	P	P	I	The LPTIM interrupt is not used in OpenSTLinux distribution. It is implemented in STM32CubeMP1 Package Src/stm32mp1xx_hal_lptim.c .
	2.9.3	LPTIM events and PWM output are delayed by 1 kernel clock cycle	P	P	TBC
RTC and TAMP	2.10.1	Alarm flag may be repeatedly set when the core is stopped in debug	A	N	TBC
	2.10.2	Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1	A	A	TBC
I2C	2.11.1	Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period	P	P	I	This workaround is implemented in TF-A fdts with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz. It is valid for both OpenSTLinux distribution and STM32CubeMP1 Package.
	2.11.2	Spurious bus error detection in master mode	A	A	N	In order to get real bus error notifications, this workaround is implemented neither within OpenSTLinux distribution nor within STM32CubeMP1 Package.
	2.11.3	OVR flag not set in underrun condition	P	N	TBC
	2.11.4	Transmission stalled after first byte transfer	A	A	N
USART	2.12.1	Anticipated end-of-transmission signaling in SPI slave mode	A	A	TBC
	2.12.2	Data corruption due to noisy receive line	A	A	TBC
	2.12.3	USART does not generate DMA requests after setting/clearing DMAT bit	A	A	TBC
SPI	2.13.1	Master data transfer stall at system clock much faster than SCK	A	A	I	SPI is disabled after each EOT in OpenSTLinux distribution drivers/spi/spi-stm32.c and in STM32CubeMP1 Package Src/stm32mp1xx_hal_spi.c .
	2.13.2	Corrupted CRC return at non-zero UDRDET setting	P	P	N	CRC is not supported in OpenSTLinux distribution. This workaround is not implemented in STM32CubeMP1 Package.
	2.13.3	TXP interrupt occurring while SPI disabled	A	A	I	This workaround is implemented in OpenSTLinux distribution, drivers/spi/spi-stm32.c ensures that all interrupts are disabled before the SPI is disabled. This workaround is implemented in STM32CubeMP1 Package Src/stm32mp1xx_hal_spi.c .
	2.13.4	Possible corruption of last-received data depending on CRCSIZE setting	A	A	N	CRC is not supported in OpenSTLinux distribution.
FDCAN	2.14.1	Desynchronization under specific condition with edge filtering enabled	A	A	N
	2.14.2	Tx FIFO messages inverted under specific buffer usage and priority setting	A	A	N
	2.14.3	DAR mode transmission failure due to lost arbitration	A	A	N
OTG	2.14.1	Host packet transmission may hang when connecting the full speed interface through a hub to a low-speed device	A	N	TBC
ETH	2.16.1	Incorrect L4 inverse filtering results for corrupted packets	A	N	TBC
	2.16.2	Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled	A	A	N
	2.16.3	Spurious receive watchdog timeout interrupt	A	A	N
	2.16.4	Incorrect flexible PPS output interval under specific conditions	A	A	N
	2.16.5	Packets dropped in RMII 10Mbps mode due to fake dribble and CRC error	A	A	N
	2.16.6	ARP offload function not effective	A	A	I	ARP software support is used in OpenSTLinux distribution.
	2.16.7	Spurious checksum error upon MTL pending Tx queue flush	A	N	TBC

5. References

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