SAES device tree configuration

Revision as of 13:04, 4 May 2022 by Registered User (Created page with "== Article purpose == The purpose of this article is to explain how to configure the SAES internal peripheral using the device tree mechanism. == DT bindi...")
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1. Article purpose[edit source]

The purpose of this article is to explain how to configure the SAES internal peripheral using the device tree mechanism.

2. DT bindings documentation[edit source]

The following binding-related documentation explains how to write device tree files for SAES:

  • OP-TEE STM32 SAES device tree bindings: documentation/devicetree/bindings/crypto/st,stm32-saes.yaml[1].

3. DT configuration[edit source]

This hardware description is a combination of STM32 microprocessor and board device tree files. See Device tree for explanations on device tree file split.

3.1. DT configuration (STM32 level)[edit source]

The SAES node is located in the STM32 MPU device tree.

3.2. DT configuration (board level)[edit source]

Board level device tree is used to enable the SAES.

4. References[edit source]

Please refer to the following links for additional information: