I2C internal peripheral

Applicable for

STM32MP13x lines, STM32MP15x lines

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1. Article purpose

The purpose of this article is to:

• briefly introduce the I2C peripheral and its main features
• indicate the level of security supported by this hardware block
• explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the I2C peripheral.

2. Peripheral overview

The I2C bus interface serves as an interface between the microcontroller and the serial I2C bus.
It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C controller allows to be a slave as well if need be.
It is also SMBus 2.0 compatible.
For more information about I2C please refer to this link: I2C wikipedia or i2c-bus.org
For more information about SMBus please refer to this link: SMBus wikipedia or i2c-bus.org

2.1. Features

Here are the main features:

• Multi-master
• Standard (100 KHz) and fast speed modes (400 KHz and Plus 1 MHz)
• I2C 10-bit address
• I2C slave capabilities (programmable I2C address)
• DMA capabilities
• SMBus 2.0 compatible
  • Standard bus protocol (quick command; byte, word, block read/write)
  • Host notification
  • Alert

Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2. Security support

2.2.1. On STM32MP13x lines 

There are five I2C instances:

• I2C instances 1 and 2 are non-secure.
• I2C instances 3, 4 and 5 can be secure (under ETZPC control).

2.2.2. On STM32MP15x lines 

There are six I2C instances:

• I2C instances 1, 2, 3 and 5 are non-secure.
• I2C instances 4 and 6 can be secure (under ETZPC control).

3. Peripheral usage and associated software

3.1. Boot time

The I2C peripheral is usually not used at boot time. But it may be used by the SSBL and/or FSBL (see Boot chain overview), for example, to configure a PMIC (see PMIC hardware components), or to access data stored in an external EEPROM.

3.2. Runtime

3.2.1. Overview

Secure instances can be allocated to:

• the Arm^® Cortex^®-A7 secure core to be controlled in OP-TEE by the OP-TEE I2C driver

All I2C instances can be allocated to:

• the Arm^® Cortex^®-A7 non-secure core to be controlled in U-Boot or Linux^® by the I2C framework

On STM32MP15x lines , all but I2C4&6 instances can be allocated to:

• the Arm^® Cortex^®-M4 to be controlled in STM32Cube MPU Package by STM32Cube I2C driver

Chapter Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2. Software frameworks

3.2.2.1. On STM32MP13x lines 

Domain	Peripheral	Software components		Comment
		OP-TEE	Linux
Low speed interface	I2C	OP-TEE I2C driver	I2C Engine framework

3.2.2.2. On STM32MP15x lines 

Domain	Peripheral	Software components			Comment
		OP-TEE	Linux	STM32Cube
Low speed interface	I2C	OP-TEE I2C driver	I2C Engine framework	STM32Cube I2C driver

3.2.3. Peripheral configuration

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

For Linux^® kernel configuration, please refer to I2C configuration.

Please refer to I2C device tree configuration for detailed information on how to configure I2C peripherals.

3.2.4. Peripheral assignment

3.2.4.1. On STM32MP13x lines 

Expand

Click on the right to expand the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Low speed interface	I2C	I2C1		☐
		I2C2		☐
		I2C3	☐	☐	Assignment (single choice)
		I2C4	☐	☐	Assignment (single choice)
		I2C5	☐	☐	Assignment (single choice)

3.2.4.2. On STM32MP15x lines 

Expand

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Low speed interface	I2C	I2C1		☐	☐	Assignment (single choice)
		I2C2		☐	☐	Assignment (single choice)
		I2C3		☐	☐	Assignment (single choice)
		I2C4	☐	☐		Assignment (single choice). Used for PMIC control on ST boards.
		I2C5		☐	☐	Assignment (single choice)
		I2C6	☐	☐		Assignment (single choice)

Inter-integrated circuit (Bi-directional 2-wire bus standard for efficient inter-IC control.)

System management bus

Direct memory access

Second stage boot loader

First stage boot loader

Power management integrated circuit

Electrically-erasable programmable read-only memory

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Open portable trusted execution environment

Das U-Boot -- the universal boot loader (see U-Boot)

Linux^® is a registered trademark of Linus Torvalds.

Microprocessor unit