1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the SRAM internal memory peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The SRAM peripheral is 256-Kbyte wide and physically near to the Cortex-M33 for optimized performances from this core. It is split into two separate banks:
- SRAM1 (128 Kbytes)
- SRAM2 (128 Kbytes)
Each bank is protected via a RISAB memory firewall allowing to define 4-Kbyte granularity regions with different access rights. Each region could be assigned to different execution contexts. Each bank also owns automatic clock gating (for power management optimization) which can be linked:
- either on one processor low power state if the bank is only assigned to this processor,
- or on system low power state if the bank is assigned to several processors.
Banks content is preserved in (LPLV)Stop1/2 low power mode but it is lost in Standby low power mode as not supplied.
Moreover, SRAM1 is protected by tamper detection circuit and is erased by hardware in case of tamper detection.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm Cortex-A processor(s), and the STM32CubeMPU Package running on the Arm Cortex-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP2 series[edit | edit source]
The ROM code uses the MCU SRAM1 to store the USB context during a boot on USB for Flash programming (with STM32CubeProgrammer).
In Cortex-A35 main processor mode, Cortex-A35 FSBL (TF-A BL2) uses SRAM1 during cold boot for:
- DDR firmware loading
- mbedTLS heap
- OTP shadow
Click on 
to expand or collapse the legend...
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Core/RAM | SRAM | SRAM1 | ✓ | ✓ | ☐ | Used during cold boot by TF-A BL2 for DDR firmware loading |
| SRAM2 | ☐ | ☐ | ||||
3.2. Runtime assignment[edit | edit source]
In Cortex-A35 main processor mode, Cortex-A35 Secure OS(OP-TEE) uses SRAM1 for:
- OTP shadow
3.2.1. On STM32MP25x lines 
[edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Core/RAM | SRAM | SRAM1 | ☑OP-TEE
☐BL31 |
☐ | ☐ | ☐ | OP-TEE populate OTP shadow region | |
| SRAM2 | ☐OP-TEE ☐BL31 |
☐ | ☐ | ☐ | ||||
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers using the SRAM peripheral for the embedded software components listed in the above tables.
- Linux: reserved memory, that is used by the dmaengine (for DMA buffers management) or RPMsg for interprocess communication with the coprocessor
- OP-TEE: OP-TEE
- STM32Cube: STM32Cube
- TF-M: TF-M
The default assignment set in STMicroelectronics distribution is in line with the platform memory mapping that can be adapted by the platform user.
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.