1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the PWR peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The PWR peripheral is used to control the device power supply configuration.
It has 6 input pins (named wakeup pins) which can be programmed to wake the system up from low power. The wakeup pins are listed with WIO prefix in the STM32MP25 Datasheet.
PWR is a RIF-aware peripheral. Each PWR feature could be assigned to the different execution context of the platform following firewall rules described in Resource Isolation Framework overview.
In the case a wakeup pin shall be used by the Cortex®-A35 non secure, it should be assigned to Cortex®-A35 that will forward wake-up event via secure services.
In addition the PWR peripheral drives 3 output hardware lines named PWR_ON, PWR_LP and PWR_CPU_ON according to platform low power mode:
- with STPMIC25, all 3 lines are used an may control regulators state depending on STPMIC25 configuration.
- In the power discrete solution they drive VDDcore which feeds the peripherals. They also control the DDR power supplies (VDD_DDR, VREF_DDR, VTT_DDR) and VDDCpu that feeds the processor.
Refer to the STM32MP25 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP2 series[edit | edit source]
Click on 
to expand or collapse the legend...
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Power & Thermal | PWR 
|
PWR | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the PWR instance.
| Feature | Boot time allocation
|
Comment | ||
|---|---|---|---|---|
| Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | ||
| Voltage monitoring | ☑ | ⬚ | ||
| RAM & low power | ☑ | ⬚ | ||
| CPU1 power control | ✓ | ☐ | ⬚ | |
| CPU2 power control | ||||
| CPU3 power control | ⬚ | ⬚ | ||
| VDD eMMC | ☐ | ⬚ | ||
| VDD SD | ☐ | ⬚ | ||
| Wake up 1 | ||||
| Wake up 2 | ||||
| Wake up 3 | ||||
| Wake up 4 | ||||
| Wake up 5 | ||||
| Wake up 6 | ||||
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP25x lines 
[edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Power & Thermal | PWR
|
PWR | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the PWR instance.
| Feature | Runtime allocation
|
Comment | ||||
|---|---|---|---|---|---|---|
| Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | ||
| Voltage monitoring | ☑OP-TEE | ⬚ | ☐ | ⬚ | ||
| RAM & low power | ☑OP-TEE | ⬚ | ☐ | ⬚ | ||
| CPU1 power control | ☑OP-TEE ☑TF-A BL31 |
⬚ | ||||
| CPU2 power control | ☑OP-TEE | ☐ if TZ_EN | ☐ if TZ_DIS | |||
| CPU3 power control | ☐OP-TEE | ☐ | ☐ | ☐ | ||
| VDD eMMC | ☑OP-TEE | ⬚ | ☐ | ☐ | ||
| VDD SD | ☑OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 1 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 2 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 3 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 4 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 5 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
| Wake up 6 | ☐OP-TEE | ⬚ | ☐ | ☐ | ||
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the PWR peripheral for the embedded software components listed in the above tables.
- Linux®: power management, regulator framework with SCMI regulators
- OP-TEE:
- TF-A:
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:
- partial device trees (pin control and clock tree) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
6. How to go further[edit | edit source]
Power overview shows the usage of PWR drivers in OpenSTlinux power management.
7. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.