HASH internal peripheral

Applicable for

STM32MP13x lines, STM32MP15x lines, STM32MP25x lines

1. Peripheral overview[edit | edit source]

The HASH peripheral is used to compute a message digest.
The HASH peripheral is also able to give the HMAC^[1] used for authentication using the same algorithm support.

1.1. On STM32MP13x lines and STM32MP25x lines [edit | edit source]

Secure Hash algorithms supports:

SHA-1 ^[2]
SHA-2 ^[3]:
- SHA-224
- SHA-256
- SHA-384
- SHA-512
- Truncated output SHA-512/224, SHA512/256
SHA-3 ^[4]:
- SHA3-224
- SHA3-256
- SHA3-384
- SHA3-512
- SHAKE128 and 256
- Keccak-based functions
HMAC support for all supported algorithm

Refer to the STM32MP13 reference manuals or STM32MP25 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

1.2. On STM32MP15x lines [edit | edit source]

Secure Hash algorithms supports:

MD5 ^[5]
SHA-1 ^[2]
SHA-2 ^[3]:
- SHA-224
- SHA-256
HMAC support for all supported algorithm

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

2. Peripheral usage[edit | edit source]

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

2.1. Boot time assignment[edit | edit source]

The HASH instance is used as boot device to support binary authentication.

2.1.1. On STM32MP13x lines [edit | edit source]

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)	Comment
Security	HASH	HASH	✓	☑

2.1.2. On STM32MP15x lines [edit | edit source]

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)	Comment
Security	HASH	HASH1	✓	☑
Security	HASH	HASH2				not used at boot time.

2.1.3. On STM32MP2 series[edit | edit source]

Click on to expand or collapse the legend...

☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 non-secure (U-Boot)	Comment
Security	HASH	HASH	✓	☑	☐

2.2. Runtime assignment[edit | edit source]

2.2.1. On STM32MP13x lines [edit | edit source]

Click on to expand or collapse the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Comment
Security	HASH	HASH	☐	☐	Assignment (single choice)

2.2.2. On STM32MP15x lines [edit | edit source]

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Security	HASH	HASH1	☐	☐		Assignment (single choice)
Security	HASH	HASH2			☐

2.2.3. On STM32MP25x lines [edit | edit source]

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
Domain	Peripheral	Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 non-secure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 non-secure (STM32Cube)	Cortex-M0+ (STM32Cube)	Comment
Security	HASH	HASH	☐^OP-TEE	☐	☐	☐

3. Software frameworks and drivers[edit | edit source]

Below are listed the software frameworks and drivers managing the HASH peripheral for the embedded software components listed in the above tables.

Linux^®: crypto framework
OP-TEE: HASH driver and Cryptographic Provider API (CP API)
STM32Cube: HASH HAL driver and header file of HASH HAL module
TF-A BL2: HASH driver

4. How to assign and configure the peripheral[edit | edit source]

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

5. References[edit | edit source]

[1] ttps://en.wikipedia.org/wiki/HMAC

[SHA-2] 2.0 ^2.1 https://en.wikipedia.org/wiki/Secure_Hash_Algorithms

[SHA2-3] 3.0 ^3.1 https://en.wikipedia.org/wiki/SHA-2

[4] ttps://en.wikipedia.org/wiki/SHA-3

[5] ttps://en.wikipedia.org/wiki/MD5

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[2]

[3]

[4]

[5]