STM32MP15 peripherals overview

This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1. Internal peripherals overview

The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several runtime contexts exist on STM32MP15 device, corresponding to the different Arm cores and associated security modes:

•  Arm dual core Cortex-A7 secure  (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
•  Arm dual core Cortex-A7 non secure , running Linux
•  Arm Cortex-M4  (non-secure), running STM32Cube

Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual may expose more possibilities than what is shown here.

STM32MP1 internal peripherals overview

2. Internal peripherals assignment

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

STM32MP15 RTC internal peripheral

3. Article purpose

The purpose of this article is to:

• briefly introduce the STGEN peripheral and its main features
• indicate the level of security supported by this hardware block
• explain how it can be allocated to the runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the STGEN peripheral.

4. Peripheral overview

The STGEN peripheral provides the reference clock used by the Arm^® Cortex^®-A7 generic timer for its counters, including the system tick generation.

It is clocked by ACLK (the AXI bus clock), so caution is needed when this clock is changed; otherwise the operating system (running on the Cortex-A7) might run with a varying reference clock.

4.1. Features

Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

4.2. Security support

The STGEN is a single-instance peripheral that can be accessed via the two following register sets:

• STGENC for the control. That is, a secure port (under ETZPC control).
• STGENR for the read-only access. That is, a non secure port.

5. Peripheral usage and associated software

5.1. Boot time

The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chain overview) once the clock tree is set up.

5.2. Runtime

5.2.1. Overview

Linux^® and OP-TEE use the Arm Cortex-A7 generic timer that gets its counter from the STGEN, but this is transparent at run time.

Hence there is no runtime allocation decision for this peripheral: both contexts are selected by default.

5.2.2. Software frameworks

5.2.2.1. On STM32MP13x lines 

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Analog	ADC	ADC		☐	☐	Assignment (single choice)
Analog	DAC	DAC		☐	☐	Assignment (single choice)
Analog	DFSDM	DFSDM		☐	☐	Assignment (single choice)
Analog	VREFBUF	VREFBUF		☐		Assignment (single choice)
Audio	SAI	SAI1		☐	☐	Assignment (single choice)
		SAI2		☐	☐	Assignment (single choice)
		SAI3		☐	☐	Assignment (single choice)
		SAI4		☐	☐	Assignment (single choice)
Audio	SPDIFRX	SPDIFRX		☐	☐	Assignment (single choice)
Coprocessor	IPCC	IPCC		☑	☑	Shared (none or both)
Coprocessor	HSEM	HSEM	✓	✓	✓

Domain	Peripheral	Software components		Comment
		OP-TEE	Linux
Core	STGEN	see comment	see comment	Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime

5.2.2.2. On STM32MP15x lines 

Domain	Peripheral	Software components			Comment
		OP-TEE	Linux	STM32Cube
Core	STGEN	see comment	see comment		Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime

5.2.4. Peripheral assignment

5.2.4.1. On STM32MP13x lines 

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Core	STGEN	STGEN	✓	✓

5.2.4.2. On STM32MP15x lines 

Expand

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Core	STGEN	STGEN	✓	✓

6. References

STM32MP15 SYSCFG internal peripheral

Core/DMA DMA DMA1 ☐ ☐ Assignment (single choice) DMA2 ☐ ☐ Assignment (single choice) Core/DMA DMAMUX DMAMUX ☐ ☐ Shareable (multiple choices supported) Core/Interrupts GIC GIC ✓ ✓ Core/Interrupts NVIC NVIC ✓ Core/RAM MCU SRAM SRAM1 ☐ ☐ ☐ Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4) SRAM2 ☐ ☐ ☐ Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4) SRAM3 ☐ ☐ ☐ Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4) SRAM4 ☐ ☐ ☐ Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4) Core/RAM RETRAM RETRAM ☐ ☐ ☐ Assignment (single choice) Core/Watchdog IWDG IWDG1 ☐ IWDG2 ☐ ☐ Shared (none or both):

• Cortex-A7 non secure for reload
• Cortex-A7 secure for early interrupt handling

Core/Watchdog WWDG WWDG ☐ High speed interface USBH (USB Host) USBH (USB Host) ☐ High speed interface USBPHYC (USB HS PHY controller) USBPHYC (USB HS PHY controller) ☐ Low speed interface I2C I2C1 ☐ ☐ Assignment (single choice) I2C2 ☐ ☐ Assignment (single choice) I2C3 ☐ ☐ Assignment (single choice) I2C4 ☐ ☐ Assignment (single choice).
Used for PMIC control on ST boards. I2C5 ☐ ☐ Assignment (single choice) I2C6 ☐ ☐ Assignment (single choice) Mass storage QUADSPI QUADSPI ☐ ☐ Assignment (single choice) Mass storage SDMMC SDMMC1 ☐ SDMMC2 ☐ SDMMC3 ☐ ☐ Assignment (single choice) Networking ETH ETH ☐ Assignment (single choice) Power & Thermal DTS DTS ☐ Power & Thermal PWR PWR ✓ ✓ ✓ STM32MP15 RCC internal peripheral STM32MP15 CRYP internal peripheral STM32MP15 ETZPC internal peripheral STM32MP15 HASH internal peripheral STM32MP15 RNG internal peripheral STM32MP15 TAMP internal peripheral Trace & Debug DBGMCU DBGMCU No assignment Trace & Debug HDP HDP ☐ ETM internal peripheral STM internal peripheral Visual CEC CEC ☐ ☐ Assignment (single choice) Visual DCMI DCMI ☐ ☐ Assignment (single choice) Visual DSI DSI ☐ Visual GPU GPU ☐ Visual LTDC LTDC ☐

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Operating system

System time generator

First stage boot loader

Linux^® is a registered trademark of Linus Torvalds.

Open portable trusted execution environment

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Digital-to-analog converter (Electronic circuit that converts a binary number into a continuously varying value.)

Digital filter for sigma-delta modulator

Voltage reference buffer (STM32 specific)

Inter-processor communication controller

Hardware semaphore

Direct memory access

Generic interrupt controller

Nested vectored interrupt controller

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

USB Host (STM32 specific)

High speed (MIPI^® alliance DSI standard)

Physical layer protocol

Power management integrated circuit

Ethernet

Device tree source (in software context) or digital temperature sensor (in peripheral context)

Hardware debug port

Consumer electronics control (HDMI standard)

Digital Camera memory interface

Display serial interface (MIPI^® Alliance standard)

Graphics processing units

LCD TFT display controller (STM32 specific)

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Operating system

System time generator

First stage boot loader

Linux^® is a registered trademark of Linus Torvalds.

Open portable trusted execution environment

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Digital-to-analog converter (Electronic circuit that converts a binary number into a continuously varying value.)

Digital filter for sigma-delta modulator

Voltage reference buffer (STM32 specific)

Inter-processor communication controller

Hardware semaphore

Direct memory access

Generic interrupt controller

Nested vectored interrupt controller

Random access memory (Early computer memories generally hadserial access. Memories where any given address can be accessed when desired were then called "random access" to distinguish them from the memories where contents can only be accessed in a fixed order. The term is used today for volatile random-acces ssemiconductor memories.)

USB Host (STM32 specific)

High speed (MIPI^® alliance DSI standard)

Physical layer protocol

Power management integrated circuit

Ethernet

Device tree source (in software context) or digital temperature sensor (in peripheral context)

Hardware debug port

Consumer electronics control (HDMI standard)

Digital Camera memory interface

Display serial interface (MIPI^® Alliance standard)

Graphics processing units

LCD TFT display controller (STM32 specific)

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

High-definition multimedia interface (HDMI standard)