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==Article purpose== | ==Article purpose== | ||
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* and a comprehensive set of IP blocks. | * and a comprehensive set of IP blocks. | ||
Arm<sup>®</sup> has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight<sup>™</sup> infrastructure.<br /> | Arm<sup>®</sup> has defined an open CoreSight<sup>™</sup>architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight<sup>™</sup> infrastructure.<br /> | ||
[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|CoreSight overview of STM32MP15. Check the [[#Features | Reference Manual]] for the other devices]] | [[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|CoreSight overview of STM32MP15. Check the [[#Features | Reference Manual]] for the other devices]] | ||
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| FPB: Flash Patch and Breakpoint || {{N}} || {{Y}} || {{Y}} | | FPB: Flash Patch and Breakpoint || {{N}} || {{Y}} || {{Y}} | ||
|- | |- | ||
| ETM: | | ETM: Embedded Trace Macrocell || {{Y}} || {{Y}} || {{Y}} | ||
|- | |- | ||
| ETF: Embedded Trace FIFO || {{Y}} || {{Y}} || {{Y}} | | ETF: Embedded Trace FIFO || {{Y}} || {{Y}} || {{Y}} | ||
| Line 61: | Line 58: | ||
| CTM: Cross Trigger Matrix || {{Y}} || {{Y}} || {{Y}} | | CTM: Cross Trigger Matrix || {{Y}} || {{Y}} || {{Y}} | ||
|- | |- | ||
| TSGEN: | | TSGEN:Timestamp Generator || {{Y}} || {{Y}} || {{Y}} | ||
|- | |- | ||
| STM: | | STM: System Trace Macrocell || {{N}} || {{Y}} || {{Y}} | ||
|- | |- | ||
|} | |} | ||
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===Features=== | ===Features=== | ||
Refer to the '''Debug support (DBG)''' chapter of [[STM32 MPU resources#Reference manuals|reference manuals]] corresponding to the STM32 MPU, you use, for the complete list of features, and to the software components, introduced above, to see which features are really implemented.<br> | |||
==Peripheral usage== | |||
Arm® CoreSight™ components can not be assigned neither at boot time nor at runtime. | |||
Arm® CoreSight™ components are accessible from external debuggers only when debug is activated, e.g. in production mode by using the [[Wrapper_for_FSBL_images | wrapper for FSBL]]. | |||
==Software frameworks and drivers== | |||
There is no embedded software dedicated to the CoreSight<sup>™</sup>internal peripheral delivered with STM32MPU ecosystem. Nevertheless, debugging tools use them through an external probe. | |||
{{ReviewsComments|-- [[User:Loic Pallardy|Loic Pallardy]] ([[User talk:Loic Pallardy|talk]]) 22:15, 6 December 2023 (CET)<br />no SW for the moment, do you agree ?}} | |||
{{ReviewsComments|[[User:Antonio Borneo|Antonio Borneo]] ([[User talk:Antonio Borneo|talk]]) 09:13, 7 December 2023 (CET)</br> Correct. For MP1x and BETA-MP25 we have no SW. It will change for sure for MM-MP25, not sure we can get also MP1x at the same time. This page will be updated for MM-MP25.}} | |||
==References== | ==References== | ||
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<noinclude> | <noinclude> | ||
[[Category:Trace and debug peripherals]] | [[Category:Trace and debug peripherals]] | ||
{{PublicationRequestId | 20002 | 2021-05-12 | }} | {{PublicationRequestId | 20002 | 2021-05-12 | }} | ||
</noinclude> | </noinclude> | ||
Latest revision as of 10:13, 7 December 2023
1. Article purpose[edit | edit source]
The purpose of this article is to provide information on the Arm® CoreSight™ hardware subsystem.
It explains what are the principle peripherals of this subsystem.
2. Peripheral overview[edit | edit source]
Arm® CoreSight™ products include
- a wide range of trace macrocells for Arm® processors,
To enable the debug and trace of the most complex, multi-core SoCs, Arm® CoreSight™ products include
- a system and software instrumentation,
- and a comprehensive set of IP blocks.
Arm® has defined an open CoreSight™architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight™ infrastructure.
2.1. Components description[edit | edit source]
The debug features are based on Arm® CoreSight™ components
| Arm® CoreSight™ components | STM32MP13x lines 
|
STM32MP15x lines
|
STM32MP25x lines
|
|---|---|---|---|
| SWJ-DP: JTAG/Serial-wire debug port |  |
|
|
| AXI-AP: AXI access port | |
|
|
| AHB-AP: AHB access port |  |
|
|
| APB-AP: APB access port | |
|
|
| ITM: Instrumentation Trace Macrocell | |
|
|
| DWT: Data Watchpoint and Trace | |
|
|
| FPB: Flash Patch and Breakpoint | |
|
|
| ETM: Embedded Trace Macrocell | |
|
|
| ETF: Embedded Trace FIFO | |
|
|
| ETR: Embedded Trace Router | |
|
|
| TPIU: Trace Port Interface Unit | |
|
|
| SWO: Serial Wire Output | |
|
|
| CTI: Cross Trigger Interface | |
|
|
| CTM: Cross Trigger Matrix | |
|
|
| TSGEN:Timestamp Generator | |
|
|
| STM: System Trace Macrocell | |
|
|
More information about these components can be found in the Arm® website [1]
2.2. Features[edit | edit source]
Refer to the Debug support (DBG) chapter of reference manuals corresponding to the STM32 MPU, you use, for the complete list of features, and to the software components, introduced above, to see which features are really implemented.
3. Peripheral usage[edit | edit source]
Arm® CoreSight™ components can not be assigned neither at boot time nor at runtime.
Arm® CoreSight™ components are accessible from external debuggers only when debug is activated, e.g. in production mode by using the wrapper for FSBL.
4. Software frameworks and drivers[edit | edit source]
There is no embedded software dedicated to the CoreSight™internal peripheral delivered with STM32MPU ecosystem. Nevertheless, debugging tools use them through an external probe.
5. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 