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<noinclude>{{ApplicableFor | <noinclude>{{ApplicableFor | ||
|MPUs list=STM32MP15x | |MPUs list=STM32MP15x | ||
|MPUs checklist=STM32MP13x, STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP25x | ||
}}</noinclude> | }}</noinclude> | ||
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* MCU SRAM3 (64 Kbytes) | * MCU SRAM3 (64 Kbytes) | ||
* MCU SRAM4 (64 Kbytes) | * MCU SRAM4 (64 Kbytes) | ||
Those banks have individual security control (see [[ | Those banks have individual security control (see [[#Runtime assignment|security support in the runtime assignment table]] below) and automatic clock gating (for power management optimization), but they are not supplied when the system goes to Standby low power mode, so their content is lost in that case. | ||
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | ||
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* '''Linux<sup>®</sup>''': [[Reserved memory|reserved memory]], that is used by the [[Dmaengine overview|dmaengine]] (for [[DMA internal peripheral|DMA]] buffers management) or [[Linux_RPMsg_framework_overview|RPMsg]] for interprocess communication with the coprocessor | * '''Linux<sup>®</sup>''': [[Reserved memory|reserved memory]], that is used by the [[Dmaengine overview|dmaengine]] (for [[DMA internal peripheral|DMA]] buffers management) or [[Linux_RPMsg_framework_overview|RPMsg]] for interprocess communication with the coprocessor | ||
* '''OP-TEE''': [[OP-TEE overview|OP-TEE]] | * '''OP-TEE''': [[STM32 MPU OP-TEE overview|OP-TEE]] | ||
* '''STM32Cube''': [[ | * '''STM32Cube''': [[STM32CubeMP15 Package architecture|STM32Cube]] | ||
Notice the '''and/or''' allocation between Cortex<sup>®</sup>-A7 non-secure and Cortex<sup>®</sup>-M4, meaning that it is possible to share banks between those cores, typically to realize inter process communication between [[Linux_RPMsg_framework_overview|RPMsg]] on Linux side and [[ | Notice the '''and/or''' allocation between Cortex<sup>®</sup>-A7 non-secure and Cortex<sup>®</sup>-M4, meaning that it is possible to share banks between those cores, typically to realize inter process communication between [[Linux_RPMsg_framework_overview|RPMsg]] on Linux side and [[STM32CubeMP15 Package architecture|OpenAMP]] on STM32Cube side.<br /> | ||
<br /> | <br /> | ||
The default assignement set in STMicroelectronics distribution is in line with the platform [[STM32MP15_RAM_mapping|memory mapping]], that can be adapted by the platform user. | The default assignement set in STMicroelectronics distribution is in line with the platform [[STM32MP15_RAM_mapping|memory mapping]], that can be adapted by the platform user. | ||
Latest revision as of 15:41, 25 July 2024
1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the MCU SRAM internal memory peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The MCU SRAM peripheral is 384-Kbyte wide and physically near to the Cortex®-M4 for optimized performances from this core. It is split into four separate banks:
- MCU SRAM1 (128 Kbytes)
- MCU SRAM2 (128 Kbytes)
- MCU SRAM3 (64 Kbytes)
- MCU SRAM4 (64 Kbytes)
Those banks have individual security control (see security support in the runtime assignment table below) and automatic clock gating (for power management optimization), but they are not supplied when the system goes to Standby low power mode, so their content is lost in that case.
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP15x lines 
[edit | edit source]
The ROM code uses the MCU SRAM1 to store the USB context during a boot on USB for Flash programming (with STM32CubeProgrammer).
Linux remoteproc framework (running on the Cortex®-A7) loads the Cortex®-M4 firmware code into the MCU SRAM, except the exception table that must be loaded in the RETRAM since the Cortex®-M4 is looking for its reset entry point at address 0x00000000. The overall memory mapping is shown in the platform memory mapping section.
Click on the right to expand the legend...
| Domain | Peripheral | Boot time allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
| Core/RAM | MCU SRAM | Any instance | ✓ | ☑ | ☐ | |
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP15x lines [edit | edit source]
Click on the right to expand the legend...
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Core/RAM | MCU SRAM | SRAM1 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) |
| SRAM2 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
| SRAM3 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
| SRAM4 | ☐ | ☐ | ☐ | Assignment (between A7 S and A7 NS / M4) Shareable (between A7 NS and M4) | ||
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the XXX peripheral for the embedded software components listed in the above tables.
- Linux®: reserved memory, that is used by the dmaengine (for DMA buffers management) or RPMsg for interprocess communication with the coprocessor
- OP-TEE: OP-TEE
- STM32Cube: STM32Cube
Notice the and/or allocation between Cortex®-A7 non-secure and Cortex®-M4, meaning that it is possible to share banks between those cores, typically to realize inter process communication between RPMsg on Linux side and OpenAMP on STM32Cube side.
The default assignement set in STMicroelectronics distribution is in line with the platform memory mapping, that can be adapted by the platform user.
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
The several SRAM banks are accessible via different address ranges in order to benefit from the Cortex-M4 multiple ports.
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 