STM32MP15 peripherals overview

Applicable for

STM32MP15x lines

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This article lists all internal peripherals embedded in STM32MP15x lines  and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1. Internal peripherals overview

The figure below shows all peripherals embedded in STM32MP15x lines , grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several execution contexts exist on STM32MP15x lines , corresponding to the different Arm cores and associated security modes:

•  Arm dual core Cortex-A7 secure  (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE at runtime
•  Arm dual core Cortex-A7 non secure , running U-Boot at boot time, and running Linux at runtime
•  Arm Cortex-M4 non-secure , running STM32Cube

Some peripherals can be strictly assigned to one execution context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several execution contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

Both the diagram below and the following summary table (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual may expose more possibilities than what is shown here.

STM32MP1 internal peripherals overview

2. Internal peripherals runtime assignment

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Core	RTC	RTC	☑	☐	☐	RTC is mandatory to resynchronize STGEN after exiting low-power modes.
Core	SYSCFG	SYSCFG	☑	☑	☑
Power & Thermal	RCC	RCC	✓	✓	✓
Security	ETZPC	ETZPC	✓	✓	⬚
Security	HASH	HASH1	☐	☐		Assignment (single choice)
		HASH2			☐
Security	RNG	RNG1	☐	☐		Assignment (single choice)
		RNG2			☐
Security	TAMP	TAMP	☐	☐	☐

3. Internal peripherals boot time assignment

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)
Core	RTC	RTC			☐
Core	SYSCFG	SYSCFG	✓	☑	☑
Power & Thermal	RCC	RCC	✓	✓	✓
Security	ETZPC	Any instance	✓	✓	✓	ETZPC configuration is set by OP-TEE
Security	HASH	HASH1	✓	☑
		HASH2				not used at boot time.
Security	RNG	RNG1		☑	☐
Security	TAMP	TAMP	✓	✓	✓

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Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)