USBPHYC internal peripheral

This message will disappear after all relevant tasks have been resolved.

Semantic MediaWiki

There are 1 incomplete or pending task to finish installation of Semantic MediaWiki. An administrator or user with sufficient rights can complete it. This should be done before adding new data to avoid inconsistencies.

1. Article purpose[edit source]

The purpose of this article is to

briefly introduce the USBPHYC peripheral and its main features
indicate the level of security supported by this hardware block
explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
explain, when necessary, how to configure the USBPHYC peripheral.

2. Peripheral overview[edit source]

The USBPHYC peripheral is a block that contains a dual port USB high-speed UTMI+ PHY and a UTMI switch. It makes the interface between:

the internal USB controllers (USBH and OTG)
the external USB physical lines (DP, DM)

2.1. Features[edit source]

The USBPHYC peripheral:

controls a two port high-speed PHY:
- Port1 connected to the USBH controller
- Port2 connected via the UTMI+switch to the USBH or to the OTG controller
sets the PLL values
performs other controls (and monitoring) on the PHY.

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2. Security support[edit source]

The USBPHYC is a non-secure peripheral.

3. Peripheral usage and associated software[edit source]

3.1. Boot time[edit source]

USBPHYC instances are boot devices that support Flash programming with STM32CubeProgrammer.

The USBPHYC peripheral is used by:

ROM code, FSBL and SSBL when using OTG in Device mode (DFU)
SSBL when using USBH

3.2. Runtime[edit source]

3.2.1. Overview[edit source]

The USBPHYC peripheral can be allocated to the the Arm^® Cortex^®-A7 non-secure core to be used under Linux^® with PHY framework.

The peripheral assignment chapter describes which peripheral instance can be assigned to which context.

3.2.2. Software frameworks[edit source]

Domain	Peripheral	Software components			Comment
Domain	Peripheral	OP-TEE	Linux	STM32Cube	Comment
High-speed interface	USBPHYC (USB HS PHY controller)		Linux PHY framework

3.2.3. Peripheral configuration[edit source]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals) according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to USBPHYC device tree configuration.

3.2.4. Peripheral assignment[edit source]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

☐ means that the peripheral can be assigned (☑) to the given runtime context.
✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
High speed interface	USBPHYC (USB HS PHY controller)	USBPHYC (USB HS PHY controller)		☐