1. Article purpose[edit source]
The purpose of this article is to:
- briefly introduce the Arm® Cortex®-A7 core and its main features
- indicate the level of security supported by this processor
2. Peripheral overview[edit source]
The Arm Cortex-A7 can be instanciated several times into a single cluster.
The STM32MP15 main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected line.
2.1. Features[edit source]
The Cortex-A7 is a 32 bits processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich OS such as Linux, with a high level of performance.
Refer to the STM32MP15 reference manuals for the complete list of features.
2.2. Security support[edit source]
The Cortex-A7 supports a non-secure and a secure modes that are defining two hardware execution contexts, so called Cortex-A7 non-secure and Cortex-A7 secure.
3. Peripheral usage and associated software[edit source]
All the software components executed by the Cortex-A7, at boot time and at runtime, are constituting the OpenSTLinux distribution.
3.1. Boot time[edit source]
As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the ROM code, that is the first stage of the boot chain, then it executes the FSBL TF-A in secure mode before jumping to the SSBL U-Boot in non-secure mode.
3.2. Runtime[edit source]
3.2.1. Overview[edit source]
The Cortex-A7 is running Linux in non-secure mode and OP-TEE in secure mode. Linux is executed in SMP mode on the dual core versions, as explained in the above.
3.2.2. Software frameworks[edit source]
| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Ecosystem | Cortex-A7 | OP-TEE | Linux | ||
3.2.3. Peripheral configuration[edit source]
The Cortex-A7 configuration is done by the various components running on it, according to build times parameters but also information coming from the device tree.
3.2.4. Peripheral assignment[edit source]
The Cortex-A7 is the main processor, supporting Cortex-A7 secure and Cortex-A7 non-secure contexts, so it cannot be assigned but it is managing all the peripherals assigned to those contexts.
4. How to go further[edit source]
Refer to Arm website[1] for more detailled information on this core.
5. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 