Difference between revisions of "Coresight device tree configuration"

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1 Article purpose[edit]

The purpose of this article is to explain how to configure the Coresight [1] when the peripheral (or peripheral associated to the framework) is assigned to Linux® OS.

The configuration is performed using the device tree mechanism [2].

2 Coresight DT bindings documentation[edit]

Coresight device tree bindings[3] describe all the required and optional properties.

3 Coresight DT configuration[edit]

Device tree is a hardware description of Coresight. This hardware description is only STM32MPU device.

3.1 Coresight DT configuration (STM32 level)[edit]

The Coresight IP blocks description are located in stm32mp157c.dtsi

  • This is a set of properties that may not vary for given STM32 device, such as: registers address, clock ...

	replicator {
		/*
		 * non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell"
		 */
		compatible = "arm,coresight-replicator";
		clocks = <&rcc CK_TRACE>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&funnel_in_port4>;
				};
			};
		};
	};

		funnel: funnel@50091000 {
			compatible = "arm,coresight-funnel", "arm,primecell";
			reg = <0x50091000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";
			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/* funnel input ports */
				port@0 {
					reg = <0>;
					funnel_in_port0: endpoint {
					  slave-mode;
					  remote-endpoint = <&stm_out_port>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_in_port1: endpoint {
					  slave-mode; /* A7-1 input */
					  remote-endpoint = <&etm1_out_port>;
					};
				};

				port@2 {
					reg = <2>;
					funnel_in_port2: endpoint {
					  slave-mode; /* A7-2 input */
					  remote-endpoint = <&etm2_out_port>;
					};
				};

				port@4 {
					reg = <4>;
					funnel_in_port4: endpoint {
					  slave-mode; /* REPLICATOR input */
					  remote-endpoint = <&replicator_out_port0>;
					};
				};

				port@5 {
					reg = <0>;
					funnel_out_port0: endpoint {
					  remote-endpoint = <&etf_in_port>;
					};
				};
			};
		};

		etf: etf@50092000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x50092000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					etf_in_port: endpoint {
						slave-mode;
						remote-endpoint = <&funnel_out_port0>;
					};
				};

				port@1 {
					reg = <0>;
					etf_out_port: endpoint {
						remote-endpoint = <&tpiu_in_port>;
					};
				};
			};
		};

		tpiu: tpiu@50093000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x50093000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			port {
				tpiu_in_port: endpoint {
					slave-mode;
					remote-endpoint = <&etf_out_port>;
				};
			};
		};

		stm: stm@500a0000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x500a0000 0x1000>, <0x90000000 0x1000000>,
			      <0x50094000 0x1000>;
			reg-names = "stm-base", "stm-stimulus-base", "cti-base";

			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					stm_out_port: endpoint {
						remote-endpoint = <&funnel_in_port0>;
					};
				};
			};
		};

		/* Cortex A7-1 */
		etm1: etm@500dc000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x500dc000 0x1000>;
			cpu = <&cpu0>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";
			port {
				etm1_out_port: endpoint {
					remote-endpoint = <&funnel_in_port1>;
				};
			};
		};

		/* Cortex A7-2 */
		etm2: etm@500dd000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x500dd000 0x1000>;
			cpu = <&cpu1>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			port {
				etm2_out_port: endpoint {
					remote-endpoint = <&funnel_in_port2>;
				};
			};
		};

4 How to configure Coresight using CubeMX[edit]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5 References[edit]



<noinclude>

{{ArticleBasedOnModel|[[Contributors:Peripheral or framework device tree configuration model]]}}
{{ArticleMainWriter|ChristopheR}}
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19== Article purpose ==
The purpose of this article is to explain how to configure the ''Coresight'' <ref name="Coresight"> [[Coresight overview|Coresight]] </ref> ''' when the peripheral ''(or peripheral associated to the framework)'' is assigned to Linux<sup>&reg;</sup> OS'''. 

The configuration is performed using the '''device tree mechanism''' <ref> [[Device tree]]</ref>.

== Coresight DT bindings documentation ==
''Coresight'' device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/arm/coresight.txt | Documentation/devicetree/bindings/arm/coresight.txt}}</ref> ''' describe all the required and optional properties.

== Coresight DT configuration ==
Device tree is a hardware description of [[Coresight overview|Coresight]]. This hardware description is only STM32MPU device.

=== Coresight DT configuration (STM32 level) ===
The Coresight IP blocks description are located in ''stm32mp157c.dtsi''
* This is a set of properties that may not vary for given STM32 device, such as: registers address, clock ...
<pre>

	replicator {
		/*
		 * non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell"
		 */
		compatible = "arm,coresight-replicator";
		clocks = <&rcc CK_TRACE>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&funnel_in_port4>;
				};
			};
		};
	};

		funnel: funnel@50091000 {
			compatible = "arm,coresight-funnel", "arm,primecell";
			reg = <0x50091000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";
			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/* funnel input ports */
				port@0 {
					reg = <0>;
					funnel_in_port0: endpoint {
					  slave-mode;
					  remote-endpoint = <&stm_out_port>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_in_port1: endpoint {
					  slave-mode; /* A7-1 input */
					  remote-endpoint = <&etm1_out_port>;
					};
				};

				port@2 {
					reg = <2>;
					funnel_in_port2: endpoint {
					  slave-mode; /* A7-2 input */
					  remote-endpoint = <&etm2_out_port>;
					};
				};

				port@4 {
					reg = <4>;
					funnel_in_port4: endpoint {
					  slave-mode; /* REPLICATOR input */
					  remote-endpoint = <&replicator_out_port0>;
					};
				};

				port@5 {
					reg = <0>;
					funnel_out_port0: endpoint {
					  remote-endpoint = <&etf_in_port>;
					};
				};
			};
		};

		etf: etf@50092000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x50092000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					etf_in_port: endpoint {
						slave-mode;
						remote-endpoint = <&funnel_out_port0>;
					};
				};

				port@1 {
					reg = <0>;
					etf_out_port: endpoint {
						remote-endpoint = <&tpiu_in_port>;
					};
				};
			};
		};

		tpiu: tpiu@50093000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x50093000 0x1000>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			port {
				tpiu_in_port: endpoint {
					slave-mode;
					remote-endpoint = <&etf_out_port>;
				};
			};
		};

		stm: stm@500a0000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x500a0000 0x1000>, <0x90000000 0x1000000>,<0x50094000 0x1000>;
			reg-names = "stm-base", "stm-stimulus-base", "cti-base";

			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					stm_out_port: endpoint {
						remote-endpoint = <&funnel_in_port0>;
					};
				};
			};
		};

		/* Cortex A7-1 */
		etm1: etm@500dc000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x500dc000 0x1000>;
			cpu = <&cpu0>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";
			port {
				etm1_out_port: endpoint {
					remote-endpoint = <&funnel_in_port1>;
				};
			};
		};

		/* Cortex A7-2 */
		etm2: etm@500dd000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x500dd000 0x1000>;
			cpu = <&cpu1>;
			clocks = <&rcc CK_TRACE>;
			clock-names = "apb_pclk";

			port {
				etm2_out_port: endpoint {
					remote-endpoint = <&funnel_in_port2>;
				};
			};
		};</pre>


== How to configure Coresight using CubeMX ==
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32|platform configuration device tree]] files.<br />

The STM32CubeMX may not support all the properties described in the above [[#Coresight DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.

==References==<references />

<noinclude>

{{ArticleBasedOnModel|[[Contributors:Peripheral or framework device tree configuration model]]}}
[[Category:Device tree configuration]]
[[Category:Embedded trace and debug]]</noinclude>

{{UnderConstruction}}
(One intermediate revision by one other user not shown)
Line 1: Line 1:
  +
== Article purpose ==
  +
The purpose of this article is to explain how to configure the ''Coresight'' <ref name="Coresight"> [[Coresight overview|Coresight]] </ref> ''' when the peripheral ''(or peripheral associated to the framework)'' is assigned to Linux<sup>&reg;</sup> OS'''.
  +
  +
The configuration is performed using the '''device tree mechanism''' <ref> [[Device tree]]</ref>.
  +
  +
== Coresight DT bindings documentation ==
  +
''Coresight'' device tree bindings<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/arm/coresight.txt | Documentation/devicetree/bindings/arm/coresight.txt}}</ref> ''' describe all the required and optional properties.
  +
  +
== Coresight DT configuration ==
  +
Device tree is a hardware description of [[Coresight overview|Coresight]]. This hardware description is only STM32MPU device.
  +
  +
=== Coresight DT configuration (STM32 level) ===
  +
The Coresight IP blocks description are located in ''stm32mp157c.dtsi''
  +
* This is a set of properties that may not vary for given STM32 device, such as: registers address, clock ...
  +
  +
<pre>
  +
replicator {
  +
/*
  +
* non-configurable replicators don't show up on the
  +
* AMBA bus.  As such no need to add "arm,primecell"
  +
*/
  +
compatible = "arm,coresight-replicator";
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
  +
ports {
  +
#address-cells = <1>;
  +
#size-cells = <0>;
  +
  +
/* replicator output ports */
  +
port@0 {
  +
reg = <0>;
  +
replicator_out_port0: endpoint {
  +
remote-endpoint = <&funnel_in_port4>;
  +
};
  +
};
  +
};
  +
};
  +
  +
funnel: funnel@50091000 {
  +
compatible = "arm,coresight-funnel", "arm,primecell";
  +
reg = <0x50091000 0x1000>;
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
ports {
  +
#address-cells = <1>;
  +
#size-cells = <0>;
  +
  +
/* funnel input ports */
  +
port@0 {
  +
reg = <0>;
  +
funnel_in_port0: endpoint {
  +
  slave-mode;
  +
  remote-endpoint = <&stm_out_port>;
  +
};
  +
};
  +
  +
port@1 {
  +
reg = <1>;
  +
funnel_in_port1: endpoint {
  +
  slave-mode; /* A7-1 input */
  +
  remote-endpoint = <&etm1_out_port>;
  +
};
  +
};
  +
  +
port@2 {
  +
reg = <2>;
  +
funnel_in_port2: endpoint {
  +
  slave-mode; /* A7-2 input */
  +
  remote-endpoint = <&etm2_out_port>;
  +
};
  +
};
  +
  +
port@4 {
  +
reg = <4>;
  +
funnel_in_port4: endpoint {
  +
  slave-mode; /* REPLICATOR input */
  +
  remote-endpoint = <&replicator_out_port0>;
  +
};
  +
};
  +
  +
port@5 {
  +
reg = <0>;
  +
funnel_out_port0: endpoint {
  +
  remote-endpoint = <&etf_in_port>;
  +
};
  +
};
  +
};
  +
};
  +
  +
etf: etf@50092000 {
  +
compatible = "arm,coresight-tmc", "arm,primecell";
  +
reg = <0x50092000 0x1000>;
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
  +
ports {
  +
#address-cells = <1>;
  +
#size-cells = <0>;
  +
  +
port@0 {
  +
reg = <0>;
  +
etf_in_port: endpoint {
  +
slave-mode;
  +
remote-endpoint = <&funnel_out_port0>;
  +
};
  +
};
  +
  +
port@1 {
  +
reg = <0>;
  +
etf_out_port: endpoint {
  +
remote-endpoint = <&tpiu_in_port>;
  +
};
  +
};
  +
};
  +
};
  +
  +
tpiu: tpiu@50093000 {
  +
compatible = "arm,coresight-tpiu", "arm,primecell";
  +
reg = <0x50093000 0x1000>;
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
  +
port {
  +
tpiu_in_port: endpoint {
  +
slave-mode;
  +
remote-endpoint = <&etf_out_port>;
  +
};
  +
};
  +
};
  +
  +
stm: stm@500a0000 {
  +
compatible = "arm,coresight-stm", "arm,primecell";
  +
reg = <0x500a0000 0x1000>, <0x90000000 0x1000000>,
  +
      <0x50094000 0x1000>;
  +
reg-names = "stm-base", "stm-stimulus-base", "cti-base";
  +
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
  +
ports {
  +
#address-cells = <1>;
  +
#size-cells = <0>;
  +
  +
port@0 {
  +
reg = <0>;
  +
stm_out_port: endpoint {
  +
remote-endpoint = <&funnel_in_port0>;
  +
};
  +
};
  +
};
  +
};
  +
  +
/* Cortex A7-1 */
  +
etm1: etm@500dc000 {
  +
compatible = "arm,coresight-etm3x", "arm,primecell";
  +
reg = <0x500dc000 0x1000>;
  +
cpu = <&cpu0>;
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
port {
  +
etm1_out_port: endpoint {
  +
remote-endpoint = <&funnel_in_port1>;
  +
};
  +
};
  +
};
  +
  +
/* Cortex A7-2 */
  +
etm2: etm@500dd000 {
  +
compatible = "arm,coresight-etm3x", "arm,primecell";
  +
reg = <0x500dd000 0x1000>;
  +
cpu = <&cpu1>;
  +
clocks = <&rcc CK_TRACE>;
  +
clock-names = "apb_pclk";
  +
  +
port {
  +
etm2_out_port: endpoint {
  +
remote-endpoint = <&funnel_in_port2>;
  +
};
  +
};
  +
};
  +
</pre>
  +
  +
== How to configure Coresight using CubeMX ==
  +
The [[STM32CubeMX]] tool can be used to configure the STM32MPU device and get the corresponding [[Device_tree#STM32|platform configuration device tree]] files.<br />
  +
The STM32CubeMX may not support all the properties described in the above [[#Coresight DT bindings documentation|DT bindings documentation]] paragraph. If so, the tool inserts '''user sections''' in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to [[STM32CubeMX]] user manual for further information.
  +
  +
==References==
  +
<references />
  +
 
<noinclude>
 
<noinclude>
 
{{ArticleBasedOnModel|[[Contributors:Peripheral or framework device tree configuration model]]}}
 
{{ArticleBasedOnModel|[[Contributors:Peripheral or framework device tree configuration model]]}}
{{ArticleMainWriter|ChristopheR}}
 
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19}}
 
 
[[Category:Device tree configuration]]
 
[[Category:Device tree configuration]]
 
[[Category:Embedded trace and debug]]
 
[[Category:Embedded trace and debug]]
 
</noinclude>
 
</noinclude>
{{UnderConstruction}}
 

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