1. Article purpose[edit | edit source]
This article explains how to configure the USBPHYC internal peripheral when it is assigned to the Linux® OS. In that case, it is controlled by the PHY framework.
The configuration is performed using the device tree mechanism.
It is used by the USBPHYC Linux driver[1] which registers the relevant information in PHY framework.
2. DT bindings documentation[edit | edit source]
USBPHYC device tree bindings[2] describe all the required and optional functions.
USBPHYC
|_ PLL
|
|_ PHY port#1 _________________ HOST controller
| _ |
| / 1|________________|
|_ PHY port#2 ----| |________________
| \_0| |
|_ UTMI switch_______| OTG controller
3. DT configuration[edit | edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)[edit | edit source]
The USBPHYC node is declared in:
It is composed of several nodes:
- root node e.g. usbphyc describes the USBPHYC hardware block parameters such as registers, clocks, resets and supplies.
- child nodes e.g. usbphyc_port0 and usbphyc_port1 describe the two high speed PHY ports: port#1 and port#2.
usbphyc: usbphyc@address {
compatible = "st,stm32mp1-usbphyc";
... /* usbphyc resources: registers, clocks, resets and supplies */
usbphyc_port0: usb-phy@0 {
... /* usbphyc HS PHY port#1 */
};
usbphyc_port1: usb-phy@1 {
... /* usbphyc HS PHY port#2 */
};
};
3.2. DT configuration (board level)[edit | edit source]
Follow the sequences described in the below chapters to configure and enable the USBPHYC on your board.
The 'usbphyc' root node must be filled in:
- Enable the USBPHYC block by setting status = "okay".
The child nodes for each port must be filled in:
- Configure the USBPHYC 3V3 regulator[5] by setting phy-supply = <&your_regulator>.
 Information
|
| USB HS PHY ports require an external 3V3 power supply to be provided at VDD3V3_USBHS pin. |
- Optional, you may configure the VBUS 5V regulator[5] by using a connector node with vbus-supply = <&your_regulator>. Have a look at connector bindings [6]
- Optional, for ecosystem release ≥ v4.0.0 , each PHY port parameters may be tuned by adding properties directly inside the child node of each port.
| Information
|
| It may be necessary to adjust the phy settings to compensate parasitics, which can be due to USB connector/receptacle, routing, ESD protection component.
Optional tuning parameter list is available in USBPHYC device tree bindings[2]. |
3.3. DT configuration example[edit | edit source]
The example below shows how to enable and configure USBPHYC ports in the board file.
For ecosystem release ≥ v4.0.0
&usbphyc {
status = "okay"; /* enable USB HS PHY controller */
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>; /* references the 3V3 voltage regulator on the user board */
st,tune-hs-dc-level = <2>; /* optional USB HS PHY port#1 tuning */
st,enable-fs-rftime-tuning;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <15>;
st,trim-hs-impedance = <1>;
st,tune-squelch-level = <3>;
st,tune-hs-rx-offset = <2>;
st,no-lsfs-sc;
connector {
compatible = "usb-a-connector";
vbus-supply = <&vbus_sw>; /* references the optional 5V voltage regulator on the user board */
};
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>; /* references the 3V3 voltage regulator on the user board */
st,tune-hs-dc-level = <2>; /* optional USB HS PHY port#2 tuning */
st,enable-fs-rftime-tuning;
st,enable-hs-rftime-reduction;
st,trim-hs-current = <15>;
st,trim-hs-impedance = <1>;
st,tune-squelch-level = <3>;
st,tune-hs-rx-offset = <2>;
st,no-lsfs-sc;
};
| Information
|
Static configuration of the UTMI switch to assign the port#2 to either USBH or OTG is done by the PHY user node[7]:
usbphyc_port1 user must configure an additional specifier for UTMI switch: 0 to select OTG, 1 to select USBH |
Abstract of the example to configure port#2, to be assigned to the USBH:
&usbh_ehci {
phys = <&usbphyc_port0>, <&usbphyc_port1 1>; /* 1: UTMI switch selects the USBH */
phy-names = "usb", "usb";
...
}
Abstract of the example to configure port#2, to be assigned to the OTG:
&usbotg_hs {
phys = <&usbphyc_port1 0>; /* 0: UTMI switch selects the OTG */
phy-names = "usb2-phy";
...
}
4. How to configure the DT using STM32CubeMX[edit | edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References[edit | edit source]
Please refer to the following links for additional information:
- ↑ drivers/phy/st/phy-stm32-usbphyc.c , STM32 USB PHY Controller driver
- ↑ 2.0 2.1 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml , USBPHYC device tree bindings
- ↑ arch/arm/boot/dts/stm32mp131.dtsi , STM32MP131 device tree file
- ↑ arch/arm/boot/dts/stm32mp151.dtsi , STM32MP151 device tree file
- ↑ 5.0 5.1 Regulator overview
- ↑ Documentation/devicetree/bindings/connector/usb-connector.yaml
- ↑ Documentation/devicetree/bindings/phy/phy-bindings.txt ,PHY generic bindings