Difference between revisions of "USART internal peripheral"

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1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the USART peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
  • explain, when needed, how to configure the USART peripheral.

2 Peripheral overview[edit]

The USART peripheral is used to interconnect STM32 MPU devices with other systems, typically via RS232 or RS485 protocols. In addition, the USART supports the Synchronous mode that can be used for smartcard interfacing or SPI master/slave operation.

The UART peripheral is similar to the USART but does not support the Synchronous mode.

High-speed data communications can be achieved by using the DMA internal peripheral for multibuffer configuration.

2.1 Features[edit]

Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

USART1 is a secure instance (under ETZPC control).
The other UARTs and USARTs are non-secure instances.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

All USART (except USART1) and UART instances are boot devices that support serial boot for Flash programming with STM32CubeProgrammer.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The STM32 MPU devices feature four USART instances (supporting both Asynchronous and Synchronous modes), and four UART instances (supporting only Asynchronous mode).

USART1 can be allocated to:

  • the Arm® Cortex®-A7 secure core to be used under OP-TEE with the USART OP-TEE driver, typically to communicate with a smartcard.


All USART and UART instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure core to be used under Linux® with the tty framework. However, the Linux® kernel supports only the UART Asynchronous mode (Synchronous mode not supported).

or

  • the Arm® Cortex®-M4 to be used with STM32Cube MPU Package with USART HAL driver. Both USART Synchronous and Asynchronous modes are supported by the STM32Cube MPU Package.


Chapter Peripheral assignment describes which peripheral instance can be assigned to which context.


3.2.2 Software frameworks[edit]

Domain Peripheral Software frameworks Comment
Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Low speed interface USART USART OP-TEE driver Linux serial/tty framework STM32Cube USART driver

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals) according to the information given in the corresponding software framework article or, for Linux in the Serial TTY device tree configuration article.

3.2.4 Peripheral assignment[edit]

Internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Low speed interface USART USART1 Assignment (single choice)
USART2 Assignment (single choice)
USART3 Assignment (single choice)
UART4 Assignment (single choice).
Used for Linux® serial console on ST boards.
UART5 Assignment (single choice)
USART6 Assignment (single choice)
UART7 Assignment (single choice)
UART8 Assignment (single choice)

4 How to go further[edit]

Additional documentation on USART peripheral is available on st.com:

  • STM32 USART training [1] presents the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter interface.
  • STM32 USART automatic baud rate detection [2] presents STM32 USART automatic baud rate detection.

5 References[edit]

  1. Please refer to stm32f7_peripheral_usart document on st.com
  2. STM32 USART automatic baud rate detection application note (AN4908)
<noinclude>

{{ArticleBasedOnModel | [[Internal peripheral article model]]}}
{{ArticleMainWriter | ErwanLR}}
{{ArticleApprovedVersion | ErwanLR | Reviewers : FabriceG,AlexandreT, NathalieS  | No previous approved version | AnneJ - 03Aug'18 - 8315 | 28Aug'18}}

[[Category:Low speed interface peripherals]]
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>

==Article purpose==
The purpose of this article is to:
* briefly introduce the USART peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain, when needed, how to configure the USART peripheral.

==Peripheral overview==
The '''USART''' peripheral is used to interconnect STM32 MPU devices with other systems, typically via RS232 or RS485 protocols. In addition, the USART supports the '''Synchronous''' mode that can be used for smartcard interfacing or SPI master/slave operation.

The '''UART''' peripheral is similar to the USART but does not support the Synchronous mode. 

High-speed data communications can be achieved by using the [[DMA internal peripheral]] for multibuffer configuration.

===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.

===Security support===
USART1 is  a '''secure''' instance (under [[ETZPC_internal_peripheral|ETZPC]] control).<br>

The other UARTs and USARTs are '''non-secure''' instances.

==Peripheral usage and associated software==
===Boot time===
All USART (except USART1) and UART instances are boot devices that support serial boot for Flash programming with [[STM32CubeProgrammer]].

===Runtime===
====Overview====

The STM32 MPU devices feature four USART instances (supporting both Asynchronous and Synchronous modes), and four UART instances (supporting only Asynchronous mode).

USART1 can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be used under OP-TEE with the [[OP-TEE_overview|USART OP-TEE driver]], typically to communicate with a smartcard.<br/>

All USART and UART instances can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with the [[Serial TTY_overview|tty framework]]. However, the Linux<sup>&reg;</sup> kernel supports only the UART Asynchronous mode (Synchronous mode not supported).
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|USART HAL driver]]. Both USART Synchronous and Asynchronous modes are supported by the STM32Cube MPU Package.

{{InternalInfo| From a hardware point of view, USART1 can be configured as a non-secure peripheral in the ETZPC. However:
* It is reset to the secure status by the RCC. This means that secure services are required to control it from Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core, which is not possible from Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 side. The clock control from non-secure world is possible starting from STM32MP15 Rev.B. However the reset control remains secure.
* The MDMA controller must be used with this instance whereas all other USART and UART instances are controlled via DMA1 or DMA2. For simplicity purposes, only the MDMA is shared between the Arm<sup>&reg;</sup>Cortex<sup>&reg;</sup>-A7 secure and the Arm<sup>&reg;</sup>Cortex<sup>&reg;</sup>-A7 non secure contexts.}}
Chapter [[#Peripheral assignment|Peripheral assignment]] describes which peripheral instance can be assigned to which context.

{{ReviewsComments| GeraldB W846: Above, the sentence "It is reset to the secure status by the RCC" was written by the technical writer but the meaning of my initial sentence was lost (I do not say that my initial sentence was perfect from english perspective  :)  ... but this version needs to be reworked and discussed with the TW)}}

====Software frameworks====
{{:Internal_peripherals_software_table_template}}
 | Low speed interface
 | [[USART_internal_peripheral|USART]]
 | [[OP-TEE_overview|USART OP-TEE driver]]
 | [[Serial TTY_overview|Linux serial/tty framework]]
 | [[STM32CubeMP1 architecture|STM32Cube USART driver]]
 |
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the [[STM32CubeMX]] tool for all internal peripherals, and then manually completed (particularly for external peripherals) according to the information given in the corresponding software framework article or, for Linux in the [[Serial TTY device tree configuration]] article.

====Peripheral assignment====

{{:Internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="8" | Low speed interface
 | rowspan="8" | [[USART_internal_peripheral|USART]]
 | USART1
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 |
 | Assignment (single choice)
 |-
 | USART2
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | USART3
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | UART4
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice). <br />Used for Linux<sup>&reg;</sup> serial console on [[:Category:Getting_started_with_STM32MP1_boards|ST boards]].
 |-
 | UART5
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | USART6
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | UART7
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-
 | UART8
 | 
 | <span title="assignable peripheral" style="font-size:21px"></span>

 | <span title="assignable peripheral" style="font-size:21px"></span>

 | Assignment (single choice)
 |-</onlyinclude>

 |}

==How to go further==
Additional documentation on USART peripheral is available on st.com:
* STM32 USART training <ref>

Please refer to '''stm32f7_peripheral_usart''' document on st.com </ref> presents the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter interface.
* STM32 USART automatic baud rate detection <ref>[http://idp.st.com/dmsdownloader/downloadServlet/DM00327191_1_0?docname=DM00327191 STM32 USART automatic baud rate detection application  note (AN4908)]</ref> presents STM32 USART automatic baud rate detection.

==References==<references/>

<noinclude>

[[Category:Low speed interface peripherals]]
{{PublicationRequestId | 8315 | 2018-08-03 | AnneJ}}
{{ArticleBasedOnModel | Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>

[[Category:ToBeAlignedWithModel]]
}}</noinclude>
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{{ArticleBasedOnModel | [[Internal peripheral article model]]}}
 
{{ArticleMainWriter | ErwanLR}}
 
{{ArticleApprovedVersion | ErwanLR | Reviewers : FabriceG,AlexandreT, NathalieS  | No previous approved version | AnneJ - 03Aug'18 - 8315 | 28Aug'18}}
 
 
[[Category:Low speed interface peripherals]]
 
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model [[Internal peripheral article model]]<br>
 
[[Category:ToBeAlignedWithModel]]
 
}}
 
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==Article purpose==
 
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{{PublicationRequestId | 8315 | 2018-08-03 | AnneJ}}
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{{ArticleBasedOnModel | Internal peripheral article model}}
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{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>
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[[Category:ToBeAlignedWithModel]]
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