- Last edited 6 months ago ago
STM internal peripheral
1 Article purpose
The purpose of this article is to:
- briefly introduce the STM peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the STM peripheral.
2 Peripheral overview
The STM peripheral is used to log STM trace into the embedded trace FIFO (ETF). This trace can include hardware events (the list is given in the STM32MP15 reference manuals) or direct 'printf like' log from the CortexTemplate:Sup-A7. Once in the ETF buffer, the trace can directly be dumped from the CortexTemplate:Sup-A7 or to the trace port interface unit (TPIU), connected to an external probe able to decode it.
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.
2.2 Security support
The STM is a non secure peripheral.
3 Peripheral usage and associated software
3.1 Boot time
The STM is not used at boot time.
The STM can be assigned to the CortexTemplate:Sup-A7 non-secure for using in Linux with coresight framework.
This driver allows to select the hardware events (listed in the STM32MP15 reference manuals) to log via the STM peripheral into the ETF and dump it in the Linux console for analysis.
3.2.2 Software frameworks
| Trace & Debug | STM | | Linux Coresight framework | | |- |}
3.2.3 Peripheral configuration
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
3.2.4 Peripheral assignment
| rowspan="1" | Trace & Debug | rowspan="1" | STM | STM | | ☐ | | |-