Last edited 11 months ago

STM32MP15 peripherals overview

Applicable for STM32MP15x lines

This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1. Internal peripherals overview[edit source]

The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several runtime contexts exist on STM32MP15 device[1], corresponding to the different Arm cores and associated security modes:

  •  Arm dual core Cortex-A7 secure  (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
  •  Arm dual core Cortex-A7 non secure , running Linux
  •  Arm Cortex-M4  (non-secure), running STM32Cube

Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

STM32MP1IPsOverview legend.png

Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.

STM32MP1 internal peripherals overview

2. Internal peripherals assignment[edit source]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned to the given runtime context.
  • means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7

Analog ADC ADC Assignment (single choice)
Analog DAC DAC Assignment (single choice)
Analog DFSDM DFSDM Assignment (single choice)
Analog VREFBUF VREFBUF Assignment (single choice)
Audio SAI SAI1 Assignment (single choice)
SAI2 Assignment (single choice)
SAI3 Assignment (single choice)
SAI4 Assignment (single choice)
Audio SPDIFRX SPDIFRX Assignment (single choice)
Coprocessor IPCC IPCC Shared (none or both)
Coprocessor HSEM HSEM
Core RTC RTC RTC is mandatory to resynchronize STGEN after exiting low-power modes.
Core/DMA DMA DMA1 Assignment (single choice)
DMA2 Assignment (single choice)
Core/DMA DMAMUX DMAMUX Shareable (multiple choices supported)
Core/DMA MDMA MDMA Shareable (multiple choices supported)
Core/Interrupts EXTI EXTI Shared
Core/Interrupts GIC GIC
Core/Interrupts NVIC NVIC
Core/IOs GPIO GPIOA-K (*) The pins can individually be shared

(*): despite they cannot be secured, the pins can be used by the secure context

GPIOZ The pins can individually be secured or shared
Core/RAM BKPSRAM BKPSRAM Assignment (single choice)
Core/RAM MCU SRAM SRAM1 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM2 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM3 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM4 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
Core/RAM RETRAM RETRAM Assignment to the Cortex-M4 if used
Core/RAM SYSRAM SYSRAM Shareable (multiple choices supported)

Secure section required for low power entry and exit

Core/Timers LPTIM LPTIM1 Assignment (single choice)
LPTIM2 Assignment (single choice)
LPTIM3 Assignment (single choice)
LPTIM4 Assignment (single choice)
LPTIM5 Assignment (single choice)
Core/Timers TIM TIM1 (APB2 group) Assignment (single choice)
TIM2 (APB1 group) Assignment (single choice)
TIM3 (APB1 group) Assignment (single choice)
TIM4 (APB1 group) Assignment (single choice)
TIM5 (APB1 group) Assignment (single choice)
TIM6 (APB1 group) Assignment (single choice)
TIM7 (APB1 group) Assignment (single choice)
TIM8 (APB2 group) Assignment (single choice)
TIM12 (APB1 group) Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
TIM13 (APB1 group) Assignment (single choice)
TIM14 (APB1 group) Assignment (single choice)
TIM15 (APB2 group) Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
TIM16 (APB2 group) Assignment (single choice)
TIM17 (APB2 group) Assignment (single choice)
Core/Watchdog IWDG IWDG1
IWDG2 Shared (none or both):
  • Cortex-A7 non secure for reload
  • Cortex-A7 secure for early interrupt handling
Core/Watchdog WWDG WWDG
High speed interface OTG (USB OTG) OTG (USB OTG)
High speed interface USBH (USB Host) USBH (USB Host)
High speed interface USBPHYC (USB HS PHY controller) USBPHYC (USB HS PHY controller)
Low speed interface I2C I2C1 Assignment (single choice)
I2C2 Assignment (single choice)
I2C3 Assignment (single choice)
I2C4 Assignment (single choice).
Used for PMIC control on ST boards.
I2C5 Assignment (single choice)
I2C6 Assignment (single choice)
Low speed interface
SPI SPI2S1 Assignment (single choice)
SPI2S2 Assignment (single choice)
SPI2S3 Assignment (single choice)
SPI4 Assignment (single choice)
SPI5 Assignment (single choice)
SPI6 Assignment (single choice)
Low speed interface USART USART1 Assignment (single choice)
USART2 Assignment (single choice)
USART3 Assignment (single choice)
UART4 Assignment (single choice).
Used for Linux® serial console on ST boards.
UART5 Assignment (single choice)
USART6 Assignment (single choice)
UART7 Assignment (single choice)
UART8 Assignment (single choice)
Mass storage FMC FMC Assignment (single choice)
Mass storage QUADSPI QUADSPI Assignment (single choice)
Mass storage SDMMC SDMMC1
SDMMC3 Assignment (single choice)
Networking ETH ETH Assignment (single choice)
Networking FDCAN FDCAN1 Assignment (single choice)
FDCAN2 Assignment (single choice)
Power & Thermal DTS DTS
Power & Thermal PWR PWR
Power & Thermal RCC RCC
Security BSEC BSEC Cortex-M4 can read BSEC shadow register (BSEC_OTP_DATAx) to read a lower OTP value
Security CRC CRC1
Security CRYP CRYP1 Assignment (single choice)
Security HASH HASH1 Assignment (single choice)
Security RNG RNG1 Assignment (single choice)
Security TZC TZC
Security TAMP TAMP
Trace & Debug HDP HDP
Trace & Debug ETM ETM0
Trace & Debug STM STM
Visual CEC CEC Assignment (single choice)
Visual DCMI DCMI Assignment (single choice)
Visual DSI DSI
Visual GPU GPU

3. References[edit source]