Difference between revisions of "STM32MP15 peripherals overview"

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Applicable for STM32MP15x lines

This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1 Internal peripherals overview[edit]

The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several runtime contexts exist on STM32MP15 device[1], corresponding to the different Arm cores and associated security modes:

  •  Arm dual core Cortex-A7 secure  (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
  •  Arm dual core Cortex-A7 non secure , running Linux
  •  Arm Cortex-M4  (non-secure), running STM32Cube


Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

STM32MP1IPsOverview legend.png

Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.


STGEN SYSCFG RTC EXTI GIC NVIC IWDG IWDG WWDG DMA DMA DMAMUX MDMA SYSRAM DDR via DDR CTRL BKPSRAM MCU SRAM MCU SRAM RETRAM TIM TIM LPTIM GPIO GPIO IPCC HSEM RCC PWR DTS DDRPERFM DBGMCU HDP STM BSEC QUADSPI FMC SDMMC FDCAN ETH SDMMC USBH OTG USBPHYC USART USART USART I2C I2C I2C SPI SPI RNG HASH ETZPC CRYP CRC TZC RNG HASH TAMP CRYP CRC GPU DSI LTDC DCMI CEC VREFBUF DAC DFSDM ADC SPI I2S SPDIFRX SAI
STM32MP1 internal peripherals overview

2 Internal peripherals assignment[edit]

Internal peripherals assignment table template 

| rowspan="1" | Analog
| rowspan="1" | ADC
| ADC
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Analog
| rowspan="1" | DAC
| DAC
| 
| ☐
| ☐
| Assignment (single choice)
|-

STM32MP15 DFSDM internal peripheral 

| rowspan="1" | Analog
| rowspan="1" | VREFBUF
| VREFBUF
| 
| ☐
|
| Assignment (single choice)
|-



| rowspan="4" | Audio
| rowspan="4" | SAI
| SAI1
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SAI2
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SAI3
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SAI4
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Audio
| rowspan="1" | SPDIFRX
| SPDIFRX
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Coprocessor
| rowspan="1" | IPCC
| IPCC
|
| ☑
| ☑
| Shared (none or both)
|-



| rowspan="1" | Coprocessor
| rowspan="1" | HSEM
| HSEM
| ✓
| ✓
| ✓
| 
|-



| rowspan="1" | Core
| rowspan="1" | RTC
| RTC
| ✓
| ✓
|
| RTC is mandatory to resynchronize  STGEN after exiting  low-power modes.
|-



| rowspan="1" | Core
| rowspan="1" | STGEN
| STGEN
| ✓
| ✓
|
|
|-



| rowspan="1" | Core
| rowspan="1" | SYSCFG
| SYSCFG
| 
| ✓
| ✓
|
|-



| rowspan="2" | Core/DMA
| rowspan="2" | DMA
| DMA1
|
| ☐
| ☐
| Assignment (single choice)
|-
| DMA2
|
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Core/DMA
| rowspan="1" | DMAMUX
| DMAMUX
|
| ☐
| ☐
| Shareable (multiple choices supported)
|-



| rowspan="1" | Core/DMA
| rowspan="1" | MDMA
| MDMA
| ☐
| ☐
|
| Shareable (multiple choices supported)
|-



| rowspan="1" | Core/Interrupts
| rowspan="1" | EXTI
| EXTI
|
| ✓
| ✓
| Shared
|-



| rowspan="1" | Core/Interrupts
| rowspan="1" | GIC
| GIC
| ✓
| ✓
|
|
|-



| rowspan="1" | Core/Interrupts
| rowspan="1" | NVIC
| NVIC
| 
|
| ✓
|
|-



| rowspan="2" | Core/IOs
| rowspan="2" | GPIO
| GPIOA-K
|
| ☐
| ☐
| Shareable (with pin granularity)
|-
| GPIOZ
| ☐
| ☐
| ☐
| Shareable (with pin granularity)
|-



| rowspan="1" | Core/RAM
| rowspan="1" | BKPSRAM
| BKPSRAM
| ☐
| ☐
|
| Assignment (single choice)
|-



| rowspan="1" | Core/RAM
| rowspan="1" | DDR via DDRCTRL
| DDR
| ✓
| ✓
|
|
|-

MCU SRAM internal memory 

| rowspan="1" | Core/RAM
| rowspan="1" | RETRAM
| RETRAM
| ☐
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Core/RAM
| rowspan="1" | SYSRAM
| SYSRAM
| ☐
| ☐
|
| Shareable (multiple choices supported)
|-



| rowspan="5" | Core/Timers
| rowspan="5" | LPTIM
| LPTIM1
|
| ☐
| ☐
| Assignment (single choice)
|-
| LPTIM2
|
| ☐
| ☐
| Assignment (single choice)
|-
| LPTIM3
|
| ☐
| ☐
| Assignment (single choice)
|-
| LPTIM4
|
| ☐
| ☐
| Assignment (single choice)
|-
| LPTIM5
|
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="14" | Core/Timers
| rowspan="14" | TIM
| TIM1 (APB2 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM2 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM3 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM4 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM5 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM6 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM7 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM8 (APB2 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM12 (APB1 group)
| ☐
| ☐
| ☐
| Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
|-
| TIM13 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM14 (APB1 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM15 (APB2 group)
| ☐
| ☐
| ☐
| Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
|-
| TIM16 (APB2 group)
|
| ☐
| ☐
| Assignment (single choice)
|-
| TIM17 (APB2 group)
|
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="2" | Core/Watchdog
| rowspan="2" | IWDG
| IWDG1
| ☐
|
|
|
|-
| IWDG2
| ☐
| ☐
| 
| Shared (none or both):
  • Cortex-A7 non secure for reload
  • Cortex-A7 secure for early interrupt handling
|-



| rowspan="1" | Core/Watchdog
| rowspan="1" | WWDG
| WWDG
|
| 
| ☐
| 
|-



| rowspan="1" | High speed interface
| rowspan="1" | OTG (USB OTG)
| OTG (USB OTG)
| 
| ☐
|
|
|-



| rowspan="1" | High speed interface
| rowspan="1" | USBH (USB Host)
| USBH (USB Host)
| 
| ☐
|
|
|-



| rowspan="1" | High speed interface
| rowspan="1" | USBPHYC (USB HS PHY controller)
| USBPHYC (USB HS PHY controller)
| 
| ☐
|
|
|-



| rowspan="6" | Low speed interface
| rowspan="6" | I2C
| I2C1
| 
| ☐
| ☐
| Assignment (single choice)
|-
| I2C2
| 
| ☐
| ☐
| Assignment (single choice)
|-
| I2C3
| 
| ☐
| ☐
| Assignment (single choice)
|-
| I2C4
| ☐ 
| ☐
|
| Assignment (single choice). 
Used for PMIC control on ST boards.
|-
| I2C5
| 
| ☐
| ☐
| Assignment (single choice)
|-
| I2C6
| ☐ 
| ☐
|
| Assignment (single choice)
|-



| rowspan="6" | Low speed interface 
or 

 audio
| rowspan="6" | SPI
| SPI2S1
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SPI2S2
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SPI2S3
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SPI4
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SPI5
| 
| ☐
| ☐
| Assignment (single choice)
|-
| SPI6
| ⬚
| ☐
|
| Assignment (single choice)
|-



| rowspan="8" | Low speed interface
| rowspan="8" | USART
| USART1
| ☐
| ☐
|
| Assignment (single choice)
|-
| USART2
| 
| ☐
| ☐
| Assignment (single choice)
|-
| USART3
| 
| ☐
| ☐
| Assignment (single choice)
|-
| UART4
| 
| ☐
| ☐
| Assignment (single choice). 
Used for Linux® serial console on ST boards.
|-
| UART5
| 
| ☐
| ☐
| Assignment (single choice)
|-
| USART6
| 
| ☐
| ☐
| Assignment (single choice)
|-
| UART7
| 
| ☐
| ☐
| Assignment (single choice)
|-
| UART8
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Mass storage
| rowspan="1" | FMC
| FMC
|
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Mass storage
| rowspan="1" | QUADSPI
| QUADSPI
|
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="3" | Mass storage
| rowspan="3" | SDMMC
| SDMMC1
| 
| ☐
|
|
|-
| SDMMC2
| 
| ☐
| 
|
|-
| SDMMC3
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Networking
| rowspan="1" | ETH
| ETH
| 
| ☐
| 
| Assignment (single choice)
|-



| rowspan="2" | Networking
| rowspan="2" | FDCAN
| FDCAN1
| 
| ☐
| ☐
| Assignment (single choice)
|-
| FDCAN2
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Power & Thermal
| rowspan="1" | DTS
| DTS
|
| ☐
|
|
|-



| rowspan="1" | Power & Thermal
| rowspan="1" | PWR
| PWR
| ✓
| ✓
| ✓
|
|-



| rowspan="1" | Power & Thermal
| rowspan="1" | RCC
| RCC
| ✓
| ✓
| ✓
|
|-



| rowspan="1" | Security
| rowspan="1" | BSEC
| BSEC
| ✓
| ✓
|
|
|-



| rowspan="2" | Security
| rowspan="2" | CRC
| CRC1
| 
| ☐
|
|
|-
| CRC2
| 
| 
| ☐
|
|-

STM32MP15 CRYP internal peripheral 

| rowspan="1" | Security
| rowspan="1" | ETZPC
| ETZPC
| ✓
| ✓
| ✓
| 
|-



| rowspan="2" | Security
| rowspan="2" | HASH
| HASH1
| ☐
| ☐
| 
| Assignment (single choice)
|-
| HASH2
| 
| 
| ☐
| 
|-



| rowspan="2" | Security
| rowspan="2" | RNG
| RNG1
| ☐
| ☐
| 
| Assignment (single choice)
|-
| RNG2
| 
| 
| ☐
| 
|-



| rowspan="1" | Security
| rowspan="1" | TZC
| TZC
| ✓
| 
|
|
|-



| rowspan="1" | Security
| rowspan="1" | TAMP
| TAMP
| ✓
| ✓
|
|
|-



| rowspan="1" | Trace & Debug
| rowspan="1" | DBGMCU
| DBGMCU
|
|
|
| No assignment
|-



| rowspan="1" | Trace & Debug
| rowspan="1" |  DDRPERFM
| DDRPERFM
| 
| ✓
|
|
|-



| rowspan="1" | Trace & Debug
| rowspan="1" | HDP
| HDP
|
| ☐
|
|
|-



| rowspan="2" | Trace & Debug
| rowspan="2" | ETM
| ETM0
| ✓
| ✓
|
|
|-
| ETM1
| ✓
| ✓
| 
|
|-



| rowspan="1" | Trace & Debug
| rowspan="1" | STM
| STM
|
| 
|
| No assignment possible 
|-



| rowspan="1" | Visual
| rowspan="1" | CEC
| CEC
| 
| ☐
| ☐
| Assignment (single choice)
|-



| rowspan="1" | Visual
| rowspan="1" | DCMI
| DCMI
| 
|☐ 
|☐ 
| Assignment (single choice)
|-



| rowspan="1" | Visual
| rowspan="1" | DSI
| DSI
| 
| ☐
|
|
|-



| rowspan="1" | Visual
| rowspan="1" | GPU
| GPU
| 
| ☐
|
|
|-



| rowspan="1" | Visual
| rowspan="1" | LTDC
| LTDC
| 
| ☐
|
|
|-

|}

3 References[edit]

  1. ↑ Getting started with STM32 MPU devices#Multiple-core architecture concepts
  2. ↑ STM32MP15 reference manuals
  3. ↑ 3.03.1 How to activate HSI and CSI oscillators calibration 



<noinclude>{{ApplicableFor
|MPUs list=STM32MP15x
|MPUs checklist=STM32MP13x, STM32MP15x
}}</noinclude>

This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.<br>

Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.
==Internal peripherals overview==
The figure below shows all '''peripherals''' embedded in STM32MP15 device, grouped per '''functional domains''' that are reused in many places of this wiki to structure the articles. <br />


Several '''runtime contexts''' exist on STM32MP15 device<ref name="STM32MPU multiple cores">[[Getting started with STM32 MPU devices#Multiple-core architecture concepts]]</ref>, corresponding to the different '''Arm cores and associated security modes''':
* <span style="color:#FFFFFF; background:{{STPink}};">&nbsp;Arm dual core Cortex-A7 secure&nbsp;</span> (Trustzone), running a Secure Monitor or Secure OS like [[OP-TEE overview|OP-TEE]]
* <span style="color:#FFFFFF; background:{{STDarkBlue}};">&nbsp;Arm dual core Cortex-A7 non secure&nbsp;</span>, running [[STM32MP15 Linux kernel overview|Linux]]
* <span style="color:#FFFFFF; background:{{STLightBlue}};">&nbsp;Arm Cortex-M4&nbsp;</span> (non-secure), running [[STM32CubeMP1 architecture|STM32Cube]]<br />

Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br />

Other ones can be '''shared''' between several runtime contexts: this is the case for system peripherals, like [[STM32MP15 PWR internal peripheral|PWR]] or [[STM32MP15 RCC internal peripheral|RCC]].<br />

The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:<br /><br />


[[File: STM32MP1IPsOverview legend.png]]<br /><br />


Both the diagram below and the following summary table (in [[#Internal peripherals assignment|Internal peripherals assignment]] chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). 
They list STMicroelectronics recommendations. The STM32MP15 reference manual <ref>[[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]]</ref>  may expose more possibilities than what is shown here.

{{
ImageMap|
Image:STM32MP1IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP1 internal peripherals overview
rect 18 113 103 141[[STGEN internal peripheral | STGEN]]
rect 18 146 103 175[[STM32MP15 SYSCFG internal peripheral | SYSCFG]]
rect 18 181 103 208[[STM32MP15 RTC internal peripheral | RTC]]
rect 123 113 206 141[[EXTI internal peripheral | EXTI]]
rect 123 146 206 175[[GIC internal peripheral | GIC]]
rect 123 181 206 208[[NVIC internal peripheral | NVIC]]
rect 229 110 314 139[[IWDG internal peripheral | IWDG]]
rect 229 146 314 173[[IWDG internal peripheral | IWDG]]
rect 229 181 314 206[[WWDG internal peripheral | WWDG]]
rect 333 144 417 172[[DMA internal peripheral | DMA]]
rect 466 144 549 172[[DMA internal peripheral | DMA]]
rect 400 111 484 138[[DMAMUX internal peripheral | DMAMUX]]
rect 400 181 484 206[[MDMA internal peripheral | MDMA]]
rect 29 241 113 268[[SYSRAM internal memory | SYSRAM]]
rect 122 241 206 268[[DDRCTRL and DDRPHYC internal peripherals| DDR via DDR CTRL]]
rect 214 241 298 268[[BKPSRAM internal memory| BKPSRAM]]
rect 307 241 392 268[[STM32MP15 MCU SRAM internal memory | MCU SRAM]]
rect 400 241 484 268[[STM32MP15 MCU SRAM internal memory | MCU SRAM]]
rect 492 241 577 268[[RETRAM internal memory| RETRAM]]
rect 28 304 113 331[[TIM internal peripheral | TIM]]
rect 122 304 207 331[[TIM internal peripheral | TIM]]
rect 214 304 298 331[[LPTIM internal peripheral | LPTIM]]
rect 400 304 484 331[[GPIO internal peripheral | GPIO]]
rect 492 304 577 331[[GPIO internal peripheral | GPIO]]
rect 352 37 438 65 [[IPCC internal peripheral | IPCC]]
rect 445 37 531 65 [[HSEM internal peripheral | HSEM]]
rect 13 415 97 442 [[STM32MP15 RCC internal peripheral | RCC]]
rect 13 448 97 474 [[STM32MP15 PWR internal peripheral | PWR]]
rect 13 480 97 508 [[DTS internal peripheral | DTS]]
rect  111 379 195 409 [[DDRPERFM internal peripheral | DDRPERFM]]
rect  111 415 195 442 [[DBGMCU internal peripheral | DBGMCU]]
rect 111 448 195 474 [[HDP internal peripheral | HDP]]
rect 111 480 195 508 [[STM internal peripheral | STM]]
rect 215 381 298 408 [[BSEC internal peripheral | BSEC]]
rect 215 415 298 442 [[QUADSPI internal peripheral | QUADSPI]]
rect 215 448 298 474 [[FMC internal peripheral | FMC]]
rect 215 480 298 508 [[SDMMC internal peripheral | SDMMC]]
rect 413 480 496 508 [[FDCAN internal peripheral | FDCAN]]
rect 501 480 584 508 [[ETH internal peripheral | ETH]]
rect 316 381 401 408 [[SDMMC internal peripheral | SDMMC]]
rect 316 415 401 442 [[USBH internal peripheral | USBH]]
rect 316 448 401 474 [[OTG internal peripheral | OTG]]
rect 316 480 401 508 [[USBPHYC internal peripheral | USBPHYC]]
rect 413 365 496 393 [[USART internal peripheral | USART]]
rect 413 400 496 426[[USART internal peripheral | USART]]
rect 501 365 585 393 [[USART internal peripheral | USART]]
rect 413 434 496 460 [[I2C internal peripheral | I2C]]
rect 501 400 585 426 [[I2C internal peripheral | I2C]]
rect 501 434 585 460 [[I2C internal peripheral | I2C]]
rect 591 365 674 393 [[SPI internal peripheral | SPI]]
rect 591 400 674 426 [[SPI internal peripheral | SPI]]
rect 708 111 792 138 [[STM32MP15 RNG internal peripheral | RNG]]
rect 800 111 883 138 [[STM32MP15 HASH internal peripheral | HASH]]
rect 616 144 700 172 [[STM32MP15 ETZPC internal peripheral | ETZPC]]
rect 708 144 792 172 [[STM32MP15 CRYP internal peripheral | CRYP]]
rect 800 144 883 172 [[CRC internal peripheral | CRC]]
rect 617 179 701 206 [[TZC internal peripheral | TZC]]
rect 708 179 792 206 [[STM32MP15 RNG internal peripheral | RNG]]
rect 800 179 883 206 [[STM32MP15 HASH internal peripheral | HASH]]
rect 617 213 701 240 [[STM32MP15 TAMP internal peripheral | TAMP]]
rect 709 213 792 240 [[STM32MP15 CRYP internal peripheral | CRYP]]
rect 800 213 883 240 [[CRC internal peripheral | CRC]]
rect 617 278 700 306 [[GPU internal peripheral | GPU]]
rect 709 278 792 306 [[DSI internal peripheral | DSI]]
rect 800 278 883 306 [[LTDC internal peripheral | LTDC]]
rect 617 312 700 338 [[DCMI internal peripheral | DCMI]]
rect 709 312 792 338 [[CEC internal peripheral | CEC]]
rect 709 400 792 426 [[STM32MP15 VREFBUF internal peripheral | VREFBUF]]
rect 800 400 883 426 [[DAC internal peripheral | DAC]]
rect 709 436 792 462 [[STM32MP15 DFSDM internal peripheral | DFSDM]]
rect 800 436 883 462 [[STM32MP15 ADC internal peripheral | ADC]]
rect 617 481 700 508 [[SPI internal peripheral | SPI I2S]]
rect 709 481 792 508 [[SPDIFRX internal peripheral | SPDIFRX]]
rect 229 110 314 139[[IWDG internal peripheral | IWDG]]
rect 800 481 883 508 [[SAI internal peripheral | SAI]]
}}

==Internal peripherals assignment==
{{:Internal_peripherals_assignment_table_template}}
{{:STM32MP15_ADC_internal_peripheral}}
{{:DAC_internal_peripheral}}
{{:STM32MP15_DFSDM_internal_peripheral}}
{{:STM32MP15_VREFBUF_internal_peripheral}}
{{#lst:SAI internal peripheral|stm32mp15}}
{{#lst:SPDIFRX internal peripheral|stm32mp15}}
{{:IPCC_internal_peripheral}}
{{:HSEM_internal_peripheral}}
{{:STM32MP15_RTC_internal_peripheral}}
{{#lst:STGEN_internal_peripheral|stm32mp15}}
{{:STM32MP15_SYSCFG_internal_peripheral}}
{{#lst:DMA_internal_peripheral|stm32mp15}}
{{#lst:DMAMUX_internal_peripheral|stm32mp15}}
{{#lst:MDMA_internal_peripheral|stm32mp15}}
{{#lst:EXTI_internal_peripheral|stm32mp15}}
{{#lst:GIC_internal_peripheral|stm32mp15}}
{{:NVIC_internal_peripheral}}
{{#lst:GPIO internal peripheral|stm32mp15}}
{{#lst:BKPSRAM internal memory|stm32mp15}}
{{#lst:DDRCTRL and DDRPHYC internal peripherals|stm32mp15}}
{{:MCU_SRAM_internal_memory}}
{{:RETRAM internal memory}}
{{#lst:SYSRAM_internal_memory|stm32mp15}}
{{#lst:LPTIM_internal_peripheral|stm32mp15}}
{{#lst:TIM_internal_peripheral|stm32mp15}}
{{#lst:IWDG_internal_peripheral|stm32mp15}}
{{:WWDG_internal_peripheral}}
{{#lst:OTG_internal_peripheral|stm32mp15}}
{{#lst:USBH_internal_peripheral|stm32mp15}}
{{#lst:USBPHYC internal peripheral|stm32mp15}}
{{#lst:I2C_internal_peripheral|stm32mp15}}
{{#lst:SPI_internal_peripheral|stm32mp15}}
{{#lst:USART_internal_peripheral|stm32mp15}}
{{#lst:FMC internal peripheral|stm32mp15}}
{{#lst:QUADSPI internal peripheral|stm32mp15}}
{{#lst:SDMMC internal peripheral|stm32mp15}}
{{#lst:ETH internal peripheral|stm32mp15}}
{{#lst:FDCAN internal peripheral|stm32mp15}}
{{#lst:DTS_internal_peripheral|stm32mp15}}
{{:STM32MP15_PWR_internal_peripheral}}
{{:STM32MP15_RCC_internal_peripheral}}
{{#lst:BSEC_internal_peripheral|stm32mp15}}
{{#lst:CRC_internal_peripheral|stm32mp15}}
{{:STM32MP15_CRYP_internal_peripheral}}
{{:STM32MP15_ETZPC_internal_peripheral}}
{{:STM32MP15_HASH_internal_peripheral}}
{{:STM32MP15_RNG_internal_peripheral}}
{{#lst:TZC_internal_peripheral|stm32mp15}}
{{:STM32MP15_TAMP_internal_peripheral}}
{{#lst:DBGMCU_internal_peripheral|stm32mp15}}
{{#lst:DDRPERFM_internal_peripheral|stm32mp15}}
{{#lst:HDP_internal_peripheral|stm32mp15}}
{{#lst:ETM_internal_peripheral|stm32mp15}}
{{:STM_internal_peripheral}}
{{:CEC_internal_peripheral}}
{{:DCMI_internal_peripheral}}
{{:DSI_internal_peripheral}}
{{:GPU_internal_peripheral}}
{{#lst:LTDC_internal_peripheral|stm32mp15}}
 |}

==References==<references/>

<noinclude>

{{PublicationRequestId | 9171 | 2018-10-17 | AlainF}}
[[Category:Peripherals overview]]
[[Category:STM32MP15]]</noinclude>
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rect 123 146 206 175[[GIC internal peripheral | GIC]]
  
rect 123 146 206 175[[GIC internal peripheral | GIC]]
 
rect 123 181 206 208[[NVIC internal peripheral | NVIC]]
  
rect 123 181 206 208[[NVIC internal peripheral | NVIC]]
  +
rect 229 110 314 139[[IWDG internal peripheral | IWDG]]
 
rect 229 146 314 173[[IWDG internal peripheral | IWDG]]
  
rect 229 146 314 173[[IWDG internal peripheral | IWDG]]
 
rect 229 181 314 206[[WWDG internal peripheral | WWDG]]
  
rect 229 181 314 206[[WWDG internal peripheral | WWDG]]
Line 101: Line 102:
 
rect 617 481 700 508 [[SPI internal peripheral | SPI I2S]]
  
rect 617 481 700 508 [[SPI internal peripheral | SPI I2S]]
 
rect 709 481 792 508 [[SPDIFRX internal peripheral | SPDIFRX]]
  
rect 709 481 792 508 [[SPDIFRX internal peripheral | SPDIFRX]]
−
rect 229 110 314 139[[IWDG internal peripheral | IWDG]]
  
 
rect 800 481 883 508 [[SAI internal peripheral | SAI]]
  
rect 800 481 883 508 [[SAI internal peripheral | SAI]]
 
}}
  
}}
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