Difference between revisions of "STM32MP15 peripherals overview"

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This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1 Internal peripherals overview[edit]

The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several runtime contexts exist on STM32MP15 device[1], corresponding to the different Arm cores and associated security modes:

  •  Arm dual core Cortex-A7 secure  (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
  •  Arm dual core Cortex-A7 non secure , running Linux
  •  Arm Cortex-M4  (non-secure), running STM32Cube


Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

STM32MP1IPsOverview legend.png

Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.


STGEN SYSCFG RTC EXTI GIC NVIC IWDG IWDG WWDG DMA DMA DMAMUX MDMA SYSRAM DDR via DDR CTRL BKPSRAM MCU SRAM MCU SRAM RETRAM TIM TIM LPTIM GPIO GPIO IPCC HSEM RCC PWR DTS DBGMCU HDP STM BSEC QUADSPI FMC SDMMC FDCAN ETH SDMMC USBH OTG USBPHYC USART USART USART I2C I2C I2C SPI SPI RNG HASH ETZPC CRYP CRC TZC RNG HASH TAMP CRYP CRC GPU DSI LTDC DCMI CEC VREFBUF DAC DFSDM ADC SPI I2S SPDIFRX SAI
STM32MP1 internal peripherals overview

2 Internal peripherals assignment[edit]

Internal peripherals assignment table template

| rowspan="1" | Analog
| rowspan="1" | ADC
| ADC
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Analog
| rowspan="1" | DAC
| DAC
| 
| 
| 
| Assignment (single choice)
|-

STM32MP15 DFSDM internal peripheral

| rowspan="1" | Analog
| rowspan="1" | VREFBUF
| VREFBUF
| 
| 
|
| Assignment (single choice)
|-


| rowspan="4" | Audio
| rowspan="4" | SAI
| SAI1
| 
| 
| 
| Assignment (single choice)
|-
| SAI2
| 
| 
| 
| Assignment (single choice)
|-
| SAI3
| 
| 
| 
| Assignment (single choice)
|-
| SAI4
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Audio
| rowspan="1" | SPDIFRX
| SPDIFRX
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Coprocessor
| rowspan="1" | IPCC
| IPCC
|
| 
| 
| Shared (none or both)
|-


| rowspan="1" | Coprocessor
| rowspan="1" | HSEM
| HSEM
| 
| 
| 
| 
|-


| rowspan="1" | Core
| rowspan="1" | RTC
| RTC
| 
| 
|
| RTC is mandatory to resynchronize  STGEN after exiting  low-power modes.
|-

3 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the STGEN peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how it can be allocated to the runtime contexts and linked to the corresponding software components
  • explain, when necessary, how to configure the STGEN peripheral.

4 Peripheral overview[edit]

The STGEN peripheral provides the reference clock used by the Arm® Cortex®-A7 generic timer for its counters, including the system tick generation.

It is clocked by ACLK (the AXI bus clock), so caution is needed when this clock is changed; otherwise the operating system (running on the Cortex-A7) might run with a varying reference clock.

4.1 Features[edit]

Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

4.2 Security support[edit]

The STGEN is a single-instance peripheral that can be accessed via the two following register sets:

  • STGENC for the control. That is, a secure port (under ETZPC control).
  • STGENR for the read-only access. That is, a non secure port.

5 Peripheral usage and associated software[edit]

5.1 Boot time[edit]

The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chain overview) once the clock tree is set up.

5.2 Runtime[edit]

5.2.1 Overview[edit]

Linux® and OP-TEE use the Arm Cortex-A7 generic timer that gets its counter from the STGEN, but this is transparent at run time.

Hence there is no runtime allocation decision for this peripheral: both contexts are selected by default.

5.2.2 Software frameworks[edit]

5.2.2.1 On STM32MP13x lines Warning.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux
Core STGEN see comment see comment Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime
5.2.2.2 On STM32MP15x lines More info.png[edit]
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core STGEN see comment see comment Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime

5.2.3 Peripheral configuration[edit]

5.2.4 Peripheral assignment[edit]

5.2.4.1 On STM32MP13x lines Warning.png[edit]

Click on the right to expand the legend...

STM32MP13IPsOverview.png

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Core STGEN STGEN
5.2.4.2 On STM32MP15x lines More info.png[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Core STGEN STGEN

6 References[edit]


| rowspan="1" | Core
| rowspan="1" | SYSCFG
| SYSCFG
| 
| 
| 
|
|-


| rowspan="2" | Core/DMA
| rowspan="2" | DMA
| DMA1
|
| 
| 
| Assignment (single choice)
|-
| DMA2
|
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Core/DMA
| rowspan="1" | DMAMUX
| DMAMUX
|
| 
| 
| Shareable (multiple choices supported)
|-


| rowspan="1" | Core/DMA
| rowspan="1" | MDMA
| MDMA
| 
| 
|
| Shareable (multiple choices supported)
|-


| rowspan="1" | Core/Interrupts
| rowspan="1" | EXTI
| EXTI
|
| 
| 
| Shared
|-


| rowspan="1" | Core/Interrupts
| rowspan="1" | GIC
| GIC
| 
| 
|
|
|-


| rowspan="1" | Core/Interrupts
| rowspan="1" | NVIC
| NVIC
| 
|
| 
|
|-


| rowspan="2" | Core/IOs
| rowspan="2" | GPIO
| GPIOA-K
|
| 
| 
| Shareable (with pin granularity)
|-
| GPIOZ
| 
| 
| 
| Shareable (with pin granularity)
|-


| rowspan="1" | Core/RAM
| rowspan="1" | BKPSRAM
| BKPSRAM
| 
| 
|
| Assignment (single choice)
|-


| rowspan="1" | Core/RAM
| rowspan="1" | DDR via DDRCTRL
| DDR
| 
| 
|
|
|-

MCU SRAM internal memory

| rowspan="1" | Core/RAM
| rowspan="1" | RETRAM
| RETRAM
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Core/RAM
| rowspan="1" | SYSRAM
| SYSRAM
| 
| 
|
| Shareable (multiple choices supported)
|-


| rowspan="5" | Core/Timers
| rowspan="5" | LPTIM
| LPTIM1
|
| 
| 
| Assignment (single choice)
|-
| LPTIM2
|
| 
| 
| Assignment (single choice)
|-
| LPTIM3
|
| 
| 
| Assignment (single choice)
|-
| LPTIM4
|
| 
| 
| Assignment (single choice)
|-
| LPTIM5
|
| 
| 
| Assignment (single choice)
|-


| rowspan="14" | Core/Timers
| rowspan="14" | TIM
| TIM1 (APB2 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM2 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM3 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM4 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM5 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM6 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM7 (APB1 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM8 (APB2 group)
|
| 
| 
| Assignment (single choice)
|-
| TIM12 (APB1 group)
| 
| 
| 
| Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[1] |- | TIM13 (APB1 group) | | | | Assignment (single choice) |- | TIM14 (APB1 group) | | | | Assignment (single choice) |- | TIM15 (APB2 group) | | | | Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[1] |- | TIM16 (APB2 group) | | | | Assignment (single choice) |- | TIM17 (APB2 group) | | | | Assignment (single choice) |-


| rowspan="2" | Core/Watchdog
| rowspan="2" | IWDG
| IWDG1
| 
|
|
|
|-
| IWDG2
| 
| 
| 
| Shared (none or both):
  • Cortex-A7 non secure for reload
  • Cortex-A7 secure for early interrupt handling
|-


| rowspan="1" | Core/Watchdog
| rowspan="1" | WWDG
| WWDG
|
| 
| 
| 
|-


| rowspan="1" | High speed interface
| rowspan="1" | OTG (USB OTG)
| OTG (USB OTG)
| 
| 
|
|
|-


| rowspan="1" | High speed interface
| rowspan="1" | USBH (USB Host)
| USBH (USB Host)
| 
| 
|
|
|-


| rowspan="1" | High speed interface
| rowspan="1" | USBPHYC (USB HS PHY controller)
| USBPHYC (USB HS PHY controller)
| 
| 
|
|
|-


| rowspan="6" | Low speed interface
| rowspan="6" | I2C
| I2C1
| 
| 
| 
| Assignment (single choice)
|-
| I2C2
| 
| 
| 
| Assignment (single choice)
|-
| I2C3
| 
| 
| 
| Assignment (single choice)
|-
| I2C4
|  
| 
|
| Assignment (single choice). 
Used for PMIC control on ST boards. |- | I2C5 | | | | Assignment (single choice) |- | I2C6 | | | | Assignment (single choice) |-


| rowspan="6" | Low speed interface 
or
audio | rowspan="6" | SPI | SPI2S1 | | | | Assignment (single choice) |- | SPI2S2 | | | | Assignment (single choice) |- | SPI2S3 | | | | Assignment (single choice) |- | SPI4 | | | | Assignment (single choice) |- | SPI5 | | | | Assignment (single choice) |- | SPI6 | | | | Assignment (single choice) |-


| rowspan="8" | Low speed interface
| rowspan="8" | USART
| USART1
| 
| 
|
| Assignment (single choice)
|-
| USART2
| 
| 
| 
| Assignment (single choice)
|-
| USART3
| 
| 
| 
| Assignment (single choice)
|-
| UART4
| 
| 
| 
| Assignment (single choice). 
Used for Linux® serial console on ST boards. |- | UART5 | | | | Assignment (single choice) |- | USART6 | | | | Assignment (single choice) |- | UART7 | | | | Assignment (single choice) |- | UART8 | | | | Assignment (single choice) |-


| rowspan="1" | Mass storage
| rowspan="1" | FMC
| FMC
|
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Mass storage
| rowspan="1" | QUADSPI
| QUADSPI
|
| 
| 
| Assignment (single choice)
|-


| rowspan="3" | Mass storage
| rowspan="3" | SDMMC
| SDMMC1
| 
| 
|
|
|-
| SDMMC2
| 
| 
| 
|
|-
| SDMMC3
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Networking
| rowspan="1" | ETH
| ETH
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="2" | Networking
| rowspan="2" | FDCAN
| FDCAN1
| 
| 
| 
| Assignment (single choice)
|-
| FDCAN2
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Power & Thermal
| rowspan="1" | DTS
| DTS
|
| 
|
|
|-


| rowspan="1" | Power & Thermal
| rowspan="1" | PWR
| PWR
| 
| 
| 
|
|-


| rowspan="1" | Power & Thermal
| rowspan="1" | RCC
| RCC
| 
| 
| 
|
|-


| rowspan="1" | Security
| rowspan="1" | BSEC
| BSEC
| 
| 
|
|
|-


| rowspan="2" | Security
| rowspan="2" | CRC
| CRC1
| 
| 
|
|
|-
| CRC2
| 
| 
| 
|
|-

STM32MP15 CRYP internal peripheral

| rowspan="1" | Security
| rowspan="1" | ETZPC
| ETZPC
| 
| 
| 
| 
|-


| rowspan="2" | Security
| rowspan="2" | HASH
| HASH1
| 
| 
| 
| Assignment (single choice)
|-
| HASH2
| 
| 
| 
| 
|-


| rowspan="2" | Security
| rowspan="2" | RNG
| RNG1
| 
| 
| 
| Assignment (single choice)
|-
| RNG2
| 
| 
| 
| 
|-


| rowspan="1" | Security
| rowspan="1" | TZC
| TZC
| 
| 
|
|
|-


| rowspan="1" | Security
| rowspan="1" | TAMP
| TAMP
| 
| 
|
|
|-


| rowspan="1" | Trace & Debug
| rowspan="1" | DBGMCU
| DBGMCU
|
|
|
| No assignment
|-


| rowspan="1" | Trace & Debug
| rowspan="1" | HDP
| HDP
|
| 
|
|
|-


| rowspan="2" | Trace & Debug
| rowspan="2" | ETM
| ETM0
| 
| 
|
|
|-
| ETM1
| 
| 
| 
|
|-


| rowspan="1" | Trace & Debug
| rowspan="1" | STM
| STM
|
| 
|
| No assignment possible 
|-


| rowspan="1" | Visual
| rowspan="1" | CEC
| CEC
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Visual
| rowspan="1" | DCMI
| DCMI
| 
| 
| 
| Assignment (single choice)
|-


| rowspan="1" | Visual
| rowspan="1" | DSI
| DSI
| 
| 
|
|
|-


| rowspan="1" | Visual
| rowspan="1" | GPU
| GPU
| 
| 
|
|
|-


| rowspan="1" | Visual
| rowspan="1" | LTDC
| LTDC
| 
| 
|
|
|-
|}

7 References[edit]



This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.<br>

Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.
==Internal peripherals overview==
The figure below shows all '''peripherals''' embedded in STM32MP15 device, grouped per '''functional domains''' that are reused in many places of this wiki to structure the articles. <br />


Several '''runtime contexts''' exist on STM32MP15 device<ref name="STM32MPU multiple cores">[[Getting started with STM32 MPU devices#Multiple-core architecture concepts]]</ref>, corresponding to the different '''Arm cores and associated security modes''':
* <span style="color:#FFFFFF; background:{{STPink}};">&nbsp;Arm dual core Cortex-A7 secure&nbsp;</span> (Trustzone), running a Secure Monitor or Secure OS like [[OP-TEE overview|OP-TEE]]
* <span style="color:#FFFFFF; background:{{STDarkBlue}};">&nbsp;Arm dual core Cortex-A7 non secure&nbsp;</span>, running [[STM32MP15 Linux kernel overview|Linux]]
* <span style="color:#FFFFFF; background:{{STLightBlue}};">&nbsp;Arm Cortex-M4&nbsp;</span> (non-secure), running [[STM32CubeMP1 architecture|STM32Cube]]<br />

Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br />

Other ones can be '''shared''' between several runtime contexts: this is the case for system peripherals, like [[STM32MP15 PWR internal peripheral|PWR]] or [[STM32MP15 RCC internal peripheral|RCC]].<br />

The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:<br /><br />


[[File: STM32MP1IPsOverview legend.png]]<br /><br />


Both the diagram below and the following summary table (in [[#Internal peripherals assignment|Internal peripherals assignment]] chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). 
They list STMicroelectronics recommendations. The STM32MP15 reference manual <ref>[[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]]</ref>  may expose more possibilities than what is shown here.

{{
ImageMap|
Image:STM32MP1IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP1 internal peripherals overview
rect 18 113 103 141[[STGEN internal peripheral | STGEN]]
rect 18 146 103 175[[STM32MP15 SYSCFG internal peripheral | SYSCFG]]
rect 18 181 103 208[[STM32MP15 RTC internal peripheral | RTC]]
rect 123 113 206 141[[EXTI internal peripheral | EXTI]]
rect 123 146 206 175[[GIC internal peripheral | GIC]]
rect 123 181 206 208[[NVIC internal peripheral | NVIC]]
rect 228 113 312 141[[IWDG internal peripheral | IWDG]]
rect 228 146 312 175[[IWDG internal peripheral | IWDG]]
rect 228 181 312 208[[WWDG internal peripheral | WWDG]]
rect 333 146 416 175[[DMA internal peripheral | DMA]]
rect 465 146 550 175[[DMA internal peripheral | DMA]]
rect 400 113 484 141[[DMAMUX internal peripheral | DMAMUX]]
rect 400 181 484 208[[MDMA internal peripheral | MDMA]]
rect 29 244 114 271[[SYSRAM internal memory | SYSRAM]]
rect 121 244 206 271[[DDRCTRL and DDRPHYC internal peripherals| DDR via DDR CTRL]]
rect 215 244 298 271[[BKPSRAM internal memory| BKPSRAM]]
rect 307 244 390 271[[MCU SRAM internal memory | MCU SRAM]]
rect 400 244 484 271[[MCU SRAM internal memory | MCU SRAM]]
rect 493 244 576 271[[RETRAM internal memory| RETRAM]]
rect 28 306 112 333[[TIM internal peripheral | TIM]]
rect 122 306 205 333[[TIM internal peripheral | TIM]]
rect 214 306 298 333[[LPTIM internal peripheral | LPTIM]]
rect 400 306 484 333[[GPIO internal peripheral | GPIO]]
rect 492 306 577 333[[GPIO internal peripheral | GPIO]]
rect 354 41 438 68 [[IPCC internal peripheral | IPCC]]
rect 447 41 531 68 [[HSEM internal peripheral | HSEM]]
rect 13 418 97 444 [[STM32MP15 RCC internal peripheral | RCC]]
rect 13 450 97 478 [[STM32MP15 PWR internal peripheral | PWR]]
rect 13 484 97 512 [[DTS internal peripheral | DTS]]
rect  112 418 195 444 [[DBGMCU internal peripheral | DBGMCU]]
rect 112 450 195 478 [[HDP internal peripheral | HDP]]
rect 112 484 195 512 [[STM internal peripheral | STM]]
rect 215 384 299 411 [[BSEC internal peripheral | BSEC]]
rect 215 418 299 444 [[QUADSPI internal peripheral | QUADSPI]]
rect 215 450 299 478 [[FMC internal peripheral | FMC]]
rect 214 484 299 512 [[SDMMC internal peripheral | SDMMC]]
rect 412 485 497 512 [[FDCAN internal peripheral | FDCAN]]
rect 501 485 585 512 [[ETH internal peripheral | ETH]]
rect 316 384 401 412 [[SDMMC internal peripheral | SDMMC]]
rect 316 418 401 445 [[USBH internal peripheral | USBH]]
rect 316 451 401 479 [[OTG internal peripheral | OTG]]
rect 316 484 401 511 [[USBPHYC internal peripheral | USBPHYC]]
rect 413 369 497 396 [[USART internal peripheral | USART]]
rect 413 402 497 430[[USART internal peripheral | USART]]
rect 502 369 586 396 [[USART internal peripheral | USART]]
rect 413 437 497 463 [[I2C internal peripheral | I2C]]
rect 502 402 586 430 [[I2C internal peripheral | I2C]]
rect 502 437 586 463 [[I2C internal peripheral | I2C]]
rect 591 369 674 396 [[SPI internal peripheral | SPI]]
rect 591 402 674 430 [[SPI internal peripheral | SPI]]
rect 709 113 792 140 [[STM32MP15 RNG internal peripheral | RNG]]
rect 800 113 883 140 [[STM32MP15 HASH internal peripheral | HASH]]
rect 617 148 700 174 [[STM32MP15 ETZPC internal peripheral | ETZPC]]
rect 709 148 792 174 [[STM32MP15 CRYP internal peripheral | CRYP]]
rect 800 148 883 174 [[CRC internal peripheral | CRC]]
rect 617 182 701 209 [[TZC internal peripheral | TZC]]
rect 709 182 792 209 [[STM32MP15 RNG internal peripheral | RNG]]
rect 800 182 883 209 [[STM32MP15 HASH internal peripheral | HASH]]
rect 617 216 701 242 [[STM32MP15 TAMP internal peripheral | TAMP]]
rect 709 216 792 242 [[STM32MP15 CRYP internal peripheral | CRYP]]
rect 800 216 884 242 [[CRC internal peripheral | CRC]]
rect 617 281 701 307 [[GPU internal peripheral | GPU]]
rect 709 281 791 307 [[DSI internal peripheral | DSI]]
rect 800 281 883 307 [[LTDC internal peripheral | LTDC]]
rect 617 314 701 341 [[DCMI internal peripheral | DCMI]]
rect 709 314 792 340 [[CEC internal peripheral | CEC]]
rect 709 402 792 430 [[STM32MP15 VREFBUF internal peripheral | VREFBUF]]
rect 800 402 883 430 [[DAC internal peripheral | DAC]]
rect 709 438 792 464 [[STM32MP15 DFSDM internal peripheral | DFSDM]]
rect 800 438 883 464 [[STM32MP15 ADC internal peripheral | ADC]]
rect 618 485 701 512 [[SPI internal peripheral | SPI I2S]]
rect 709 485 792 512 [[SPDIFRX internal peripheral | SPDIFRX]]
rect 800 485 883 512 [[SAI internal peripheral | SAI]]
}}

==Internal peripherals assignment==
{{:Internal_peripherals_assignment_table_template}}
{{:STM32MP15_ADC_internal_peripheral}}
{{:DAC_internal_peripheral}}
{{:STM32MP15_DFSDM_internal_peripheral}}
{{:STM32MP15_VREFBUF_internal_peripheral}}
{{#lst:SAI internal peripheral|stm32mp15}}
{{#lst:SPDIFRX internal peripheral|stm32mp15}}
{{:IPCC_internal_peripheral}}
{{:HSEM_internal_peripheral}}
{{:STM32MP15_RTC_internal_peripheral}}
{{:STGEN_internal_peripheral}}
{{:STM32MP15_SYSCFG_internal_peripheral}}
{{#lst:DMA_internal_peripheral|stm32mp15}}
{{#lst:DMAMUX_internal_peripheral|stm32mp15}}
{{#lst:MDMA_internal_peripheral|stm32mp15}}
{{#lst:EXTI_internal_peripheral|stm32mp15}}
{{#lst:GIC_internal_peripheral|stm32mp15}}
{{:NVIC_internal_peripheral}}
{{#lst:GPIO internal peripheral|stm32mp15}}
{{#lst:BKPSRAM internal memory|stm32mp15}}
{{#lst:DDRCTRL and DDRPHYC internal peripherals|stm32mp15}}
{{:MCU_SRAM_internal_memory}}
{{:RETRAM internal memory}}
{{#lst:SYSRAM_internal_memory|stm32mp15}}
{{#lst:LPTIM_internal_peripheral|stm32mp15}}
{{#lst:TIM_internal_peripheral|stm32mp15}}
{{#lst:IWDG_internal_peripheral|stm32mp15}}
{{:WWDG_internal_peripheral}}
{{#lst:OTG_internal_peripheral|stm32mp15}}
{{#lst:USBH_internal_peripheral|stm32mp15}}
{{#lst:USBPHYC internal peripheral|stm32mp15}}
{{#lst:I2C_internal_peripheral|stm32mp15}}
{{#lst:SPI_internal_peripheral|stm32mp15}}
{{#lst:USART_internal_peripheral|stm32mp15}}
{{#lst:FMC internal peripheral|stm32mp15}}
{{#lst:QUADSPI internal peripheral|stm32mp15}}
{{#lst:SDMMC internal peripheral|stm32mp15}}
{{#lst:ETH internal peripheral|stm32mp15}}
{{#lst:FDCAN internal peripheral|stm32mp15}}
{{#lst:DTS_internal_peripheral|stm32mp15}}
{{:STM32MP15_PWR_internal_peripheral}}
{{:STM32MP15_RCC_internal_peripheral}}
{{#lst:BSEC_internal_peripheral|stm32mp15}}
{{#lst:CRC_internal_peripheral|stm32mp15}}
{{:STM32MP15_CRYP_internal_peripheral}}
{{:STM32MP15_ETZPC_internal_peripheral}}
{{:STM32MP15_HASH_internal_peripheral}}
{{:STM32MP15_RNG_internal_peripheral}}
{{#lst:TZC_internal_peripheral|stm32mp15}}
{{:STM32MP15_TAMP_internal_peripheral}}
{{#lst:DBGMCU_internal_peripheral|stm32mp15}}
{{#lst:HDP_internal_peripheral|stm32mp15}}
{{#lst:ETM_internal_peripheral|stm32mp15}}
{{:STM_internal_peripheral}}
{{:CEC_internal_peripheral}}
{{:DCMI_internal_peripheral}}
{{:DSI_internal_peripheral}}
{{:GPU_internal_peripheral}}
{{#lst:LTDC_internal_peripheral|stm32mp15}}
 |}

==References==<references/>

<noinclude>

{{PublicationRequestId | 9171 | 2018-10-17 | AlainF}}
[[Category:Peripherals overview]]
[[Category:STM32MP15]]</noinclude>
Line 11: Line 11:
 
<br />
 
<br />
 
Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br />
 
Some peripherals can be strictly '''assigned''' to one runtime context: this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br />
Other ones can be '''shared''' between several runtime contexts: this is the case for system peripherals, like [[PWR internal peripheral|PWR]] or [[RCC internal peripheral|RCC]].<br />
+
Other ones can be '''shared''' between several runtime contexts: this is the case for system peripherals, like [[STM32MP15 PWR internal peripheral|PWR]] or [[STM32MP15 RCC internal peripheral|RCC]].<br />
 
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:
 
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:
 
<br /><br />
 
<br /><br />
Line 81: Line 81:
 
rect 800 148 883 174 [[CRC internal peripheral | CRC]]
 
rect 800 148 883 174 [[CRC internal peripheral | CRC]]
 
rect 617 182 701 209 [[TZC internal peripheral | TZC]]
 
rect 617 182 701 209 [[TZC internal peripheral | TZC]]
rect 709 182 792 209 [[RNG internal peripheral | RNG]]
+
rect 709 182 792 209 [[STM32MP15 RNG internal peripheral | RNG]]
rect 800 182 883 209 [[HASH internal peripheral | HASH]]
+
rect 800 182 883 209 [[STM32MP15 HASH internal peripheral | HASH]]
 
rect 617 216 701 242 [[STM32MP15 TAMP internal peripheral | TAMP]]
 
rect 617 216 701 242 [[STM32MP15 TAMP internal peripheral | TAMP]]
rect 709 216 792 242 [[CRYP internal peripheral | CRYP]]
+
rect 709 216 792 242 [[STM32MP15 CRYP internal peripheral | CRYP]]
 
rect 800 216 884 242 [[CRC internal peripheral | CRC]]
 
rect 800 216 884 242 [[CRC internal peripheral | CRC]]
 
rect 617 281 701 307 [[GPU internal peripheral | GPU]]
 
rect 617 281 701 307 [[GPU internal peripheral | GPU]]