Difference between revisions of "STM32MP15 peripherals overview"

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SUMMARY
Applicable for STM32MP15x lines

This article lists all internal peripherals embedded in STM32MP15 device and shows the assignment possibilities to the runtime contexts for each one of them.
Via this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

Contents

1 Internal peripherals overview

  • 2 Internal peripherals assignment
  • 3 Article purpose
  • 4 Peripheral overview
  • 5 Peripheral usage and associated software
  • 5.1 Boot time
  • 5.2 Runtime
  • 5.2.1 Overview
  • 5.2.2 Software frameworks 5.2.2.1 On STM32MP13x lines 5.2.2.2 On STM32MP15x lines 
  • 5.2.3 Peripheral configuration
  • 5.2.4 Peripheral assignment 5.2.4.1 On STM32MP13x lines 5.2.4.2 On STM32MP15x lines 
  • 6 How to go further
  • 7 References
  • 8 Article purpose
  • 9 Peripheral overview
  • 10 Peripheral usage and associated software
  • 10.1 Boot time
  • 10.2 Runtime
  • 10.2.1 Overview
  • 10.2.2 Software frameworks 10.2.2.1 On STM32MP13x lines 10.2.2.2 On STM32MP15x lines 
  • 10.2.3 Peripheral configuration
  • 10.2.4 Peripheral assignment 10.2.4.1 On STM32MP13x lines 10.2.4.2 On STM32MP15x lines 
  • 11 How to go further
  • 12 References
  • 13 Article purpose
  • 14 Peripheral overview
  • 15 Peripheral usage and associated software
  • 15.1 Boot time
  • 15.2 Runtime
  • 15.2.1 Overview
  • 15.2.2 Software frameworks 15.2.2.1 On STM32MP13x lines 15.2.2.2 On STM32MP15x lines 
  • 15.2.3 Peripheral configuration
  • 15.2.4 Peripheral assignment 15.2.4.1 On STM32MP13x lines 15.2.4.2 On STM32MP15x lines 
  • 16 How to go further
  • 17 References
  • 18 Article purpose
  • 19 Peripheral overview
  • 20 Peripheral usage and associated software
  • 20.1 Boot time
  • 20.2 Runtime
  • 20.2.1 Overview
  • 20.2.2 Software frameworks 20.2.2.1 On STM32MP13x lines 20.2.2.2 On STM32MP15x lines 
  • 20.2.3 Peripheral configuration
  • 20.2.4 Peripheral assignment 20.2.4.1 On STM32MP13x lines 20.2.4.2 On STM32MP15x lines 
  • 21 References
  • 22 Article purpose
  • 23 Peripheral overview
  • 23.1 Features
  • 23.2 Security support 23.2.1 On STM32MP13x lines 23.2.2 On STM32MP15x lines 24 Peripheral usage and associated software
  • 24.1 Boot time
  • 24.2 Runtime 24.2.1 Overview 24.2.1.1 On STM32MP13x lines 24.2.1.2 On STM32MP15x lines 24.2.2 Software frameworks 24.2.2.1 On STM32MP13x lines 24.2.2.2 On STM32MP15x lines 
  • 24.2.3 Peripheral configuration
  • 24.2.4 Peripheral assignment 24.2.4.1 On STM32MP13x lines 24.2.4.2 On STM32MP15x lines 
  • 25 References
  • 26 Article purpose
  • 27 Peripheral overview
  • 27.1 Features
  • 27.2 Security support 27.2.1 On STM32MP13x lines 27.2.2 On STM32MP15x lines 28 Peripheral usage and associated software
  • 28.1 Boot time
  • 28.2 Runtime 28.2.1 Overview 28.2.1.1 On STM32MP13x lines 28.2.1.2 On STM32MP15x lines 28.2.2 Software frameworks 28.2.2.1 On STM32MP13x lines 28.2.2.2 On STM32MP15x lines 
  • 28.2.3 Peripheral configuration
  • 28.2.4 Peripheral assignment 28.2.4.1 On STM32MP13x lines 28.2.4.2 On STM32MP15x lines 
  • 29 Article purpose
  • 30 Peripheral overview
  • 31 Peripheral usage and associated software
  • 31.1 Boot time
  • 31.2 Runtime
  • 31.2.1 Overview
  • 31.2.2 Software frameworks 31.2.2.1 On STM32MP13x lines 31.2.2.2 On STM32MP15x lines 
  • 31.2.3 Peripheral configuration
  • 31.2.4 Peripheral assignment 31.2.4.1 On STM32MP13x lines 31.2.4.2 On STM32MP15x lines 
  • 32 Peripheral overview
  • 33 Peripheral usage and associated software 33.1 Boot time 33.1.1 On STM32MP15x lines 33.2 Runtime 33.2.1 Overview 33.2.1.1 On STM32MP13x lines 33.2.1.2 On STM32MP15x lines 33.2.2 Software frameworks 33.2.2.1 On STM32MP13x lines 33.2.2.2 On STM32MP15x lines 
  • 33.2.3 Peripheral configuration
  • 33.2.4 Peripheral assignment 33.2.4.1 On STM32MP13x lines 33.2.4.2 On STM32MP15x lines 
  • 34 Article purpose
  • 35 Peripheral overview
  • 36 Peripheral usage and associated software
  • 36.1 Boot time
  • 36.2 Runtime
  • 36.2.1 Overview
  • 36.2.2 Software frameworks 36.2.2.1 On STM32MP13x lines 36.2.2.2 On STM32MP15x lines 
  • 36.2.3 Peripheral configuration
  • 36.2.4 Peripheral assignment 36.2.4.1 On STM32MP13x lines 36.2.4.2 On STM32MP15x lines 
  • 37 Article purpose
  • 38 Peripheral overview
  • 38.1 Features
  • 38.2 Security support 38.2.1 On STM32MP13x lines 38.2.2 On STM32MP15x lines 39 Peripheral usage and associated software
  • 39.1 Boot time
  • 39.2 Runtime
  • 39.2.1 Overview
  • 39.2.2 Software frameworks 39.2.2.1 On STM32MP13x lines 39.2.2.2 On STM32MP15x lines 
  • 39.2.3 Peripheral configuration
  • 39.2.4 Peripheral assignment 39.2.4.1 On STM32MP13x lines 39.2.4.2 On STM32MP15x lines 
  • 40 How to go further
  • 41 References
  • 42 Peripheral overview
  • 43 Peripheral usage and associated software
  • 43.1 Boot time
  • 43.2 Runtime
  • 43.2.1 Overview
  • 43.2.2 Software frameworks 43.2.2.1 On STM32MP13x lines 43.2.2.2 On STM32MP15x lines 
  • 43.2.3 Peripheral configuration
  • 43.2.4 Peripheral assignment 43.2.4.1 On STM32MP13x lines 43.2.4.2 On STM32MP15x lines 
  • 44 References
  • 45 Article purpose
  • 46 Peripheral overview
  • 47 Peripheral usage and associated software
  • 47.1 Boot time
  • 47.2 Runtime
  • 47.2.1 Overview
  • 47.2.2 Software frameworks 47.2.2.1 On STM32MP13x lines 47.2.2.2 On STM32MP15x lines 
  • 47.2.3 Peripheral configuration
  • 47.2.4 Peripheral assignment 47.2.4.1 On STM32MP13x lines 47.2.4.2 On STM32MP15x lines 
  • 48 References
  • 49 Article purpose
  • 50 Peripheral overview
  • 51 Peripheral usage and associated software 51.1 Boot time 51.1.1 On STM32MP13x lines 51.1.2 On STM32MP15x lines 51.2 Runtime
  • 51.2.1 Overview
  • 51.2.2 Software frameworks 51.2.2.1 On STM32MP13x lines 51.2.2.2 On STM32MP15x lines 
  • 51.2.3 Peripheral configuration
  • 51.2.4 Peripheral assignment 51.2.4.1 On STM32MP13x lines 51.2.4.2 On STM32MP15x lines 
  • 52 References
  • 53 Article purpose
  • 54 Peripheral overview
  • 54.1 Features
  • 54.2 Security support 54.2.1 On STM32MP13x lines 54.2.2 On STM32MP15x lines 55 Peripheral usage and associated software
  • 55.1 Boot time
  • 55.2 Runtime 55.2.1 Overview 55.2.1.1 On STM32MP13x lines 55.2.1.2 On STM32MP15x lines 55.2.2 Software frameworks 55.2.2.1 On STM32MP13x lines 55.2.2.2 On STM32MP15x lines 
  • 55.2.3 Peripheral configuration
  • 55.2.4 Peripheral assignment 55.2.4.1 On STM32MP13x lines 55.2.4.2 On STM32MP15x lines 
  • 56 References
  • 57 Article purpose
  • 58 Peripheral overview
  • 58.1 Features
  • 58.2 Security support 58.2.1 On STM32MP13x lines 58.2.2 On STM32MP15x lines 59 Peripheral usage and associated software
  • 59.1 Boot time
  • 59.2 Runtime 59.2.1 Overview 59.2.1.1 On STM32MP13x lines 59.2.1.2 On STM32MP15x lines 59.2.2 Software frameworks 59.2.2.1 On STM32MP13x lines 59.2.2.2 On STM32MP15x lines 
  • 59.2.3 Peripheral configuration
  • 59.2.4 Peripheral assignment 59.2.4.1 On STM32MP13x lines 59.2.4.2 On STM32MP15x lines 
  • 60 How to go further
  • 61 References
  • 62 Peripheral overview
  • 63 Peripheral usage and associated software
  • 63.1 Boot time
  • 63.2 Runtime
  • 63.2.1 Overview
  • 63.2.2 Software frameworks 63.2.2.1 On STM32MP13x lines 63.2.2.2 On STM32MP15x lines 
  • 63.2.3 Peripheral configuration
  • 63.2.4 Peripheral assignment 63.2.4.1 On STM32MP13x lines 63.2.4.2 On STM32MP15x lines 
  • 64 Article purpose
  • 65 Peripheral overview
  • 65.1 Features
  • 65.2 Security support 65.2.1 On STM32MP13x lines 65.2.2 On STM32MP15x lines 66 Peripheral usage and associated software
  • 66.1 Boot time
  • 66.2 Runtime
  • 66.2.1 Overview
  • 66.2.2 Software frameworks 66.2.2.1 On STM32MP13x lines 66.2.2.2 On STM32MP15x lines 
  • 66.2.3 Peripheral configuration
  • 66.2.4 Peripheral assignment 66.2.4.1 On STM32MP13x lines 66.2.4.2 On STM32MP15x lines 
  • 67 References
  • 68 Article purpose
  • 69 Peripheral overview
  • 70 Peripheral usage and associated software
  • 70.1 Boot time
  • 70.2 Runtime
  • 70.2.1 Overview
  • 70.2.2 Software frameworks 70.2.2.1 On STM32MP13x lines 70.2.2.2 On STM32MP15x lines 
  • 70.2.3 Peripheral configuration
  • 70.2.4 Peripheral assignment 70.2.4.1 On STM32MP13x lines 70.2.4.2 On STM32MP15x lines 
  • 71 References
  • 72 Article purpose
  • 73 Peripheral overview
  • 73.1 Features
  • 73.2 Security support 73.2.1 On STM32MP13x lines 73.2.2 On STM32MP15x lines 74 Peripheral usage and associated software
  • 74.1 Boot time
  • 74.2 Runtime
  • 74.2.1 Overview
  • 74.2.2 Software frameworks 74.2.2.1 On STM32MP13x lines 74.2.2.2 On STM32MP15x lines 
  • 74.2.3 Peripheral configuration
  • 74.2.4 Peripheral assignment 74.2.4.1 On STM32MP13x lines 74.2.4.2 On STM32MP15x lines 
  • 75 Article purpose
  • 76 Peripheral overview
  • 76.1 Features
  • 76.2 Security support 76.2.1 On STM32MP13x lines 76.2.2 On STM32MP15x lines 77 Peripheral usage and associated software
  • 77.1 Boot time
  • 77.2 Runtime
  • 77.2.1 Overview
  • 77.2.2 Software frameworks 77.2.2.1 On STM32MP13x lines 77.2.2.2 On STM32MP15x lines 
  • 77.2.3 Peripheral configuration
  • 77.2.4 Peripheral assignment 77.2.4.1 On STM32MP13x lines 77.2.4.2 On STM32MP15x lines 
  • 78 References
  • 79 Article purpose
  • 80 Peripheral overview
  • 80.1 Features
  • 80.2 Security support 80.2.1 On STM32MP13x lines 80.2.2 On STM32MP15x lines 81 Peripheral usage and associated software
  • 81.1 Boot time
  • 81.2 Runtime
  • 81.2.1 Overview
  • 81.2.2 Software frameworks 81.2.2.1 On STM32MP13x lines 81.2.2.2 On STM32MP15x lines 
  • 81.2.3 Peripheral configuration
  • 81.2.4 Peripheral assignment 81.2.4.1 On STM32MP13x lines 81.2.4.2 On STM32MP15x lines 
  • 82 References
  • 83 Article purpose
  • 84 Peripheral overview
  • 84.1 Features
  • 84.2 Security support 84.2.1 On STM32MP13x lines 84.2.2 On STM32MP15x lines 85 Peripheral usage and associated software
  • 85.1 Boot time
  • 85.2 Runtime
  • 85.2.1 Overview
  • 85.2.2 Software frameworks 85.2.2.1 On STM32MP13x lines 85.2.2.2 On STM32MP15x lines 
  • 85.2.3 Peripheral configuration
  • 85.2.4 Peripheral assignment 85.2.4.1 On STM32MP13x lines 85.2.4.2 On STM32MP15x lines 
  • 86 How to go further
  • 87 References
  • 88 Article purpose
  • 89 Peripheral overview
  • 89.1 NOR/PSRAM memory controller (or external bus interface controller)
  • 89.2 NAND Flash controller
  • 89.3 Features
  • 89.4 Security support 89.4.1 On STM32MP13x lines 89.4.2 On STM32MP15x lines 90 Peripheral usage and associated software
  • 90.1 Boot time
  • 90.2 Runtime
  • 90.2.1 Overview
  • 90.2.2 Software frameworks 90.2.2.1 On STM32MP13x lines 90.2.2.2 On STM32MP15x lines 
  • 90.2.3 Peripheral configuration
  • 90.2.4 Peripheral assignment 90.2.4.1 On STM32MP13x lines 90.2.4.2 On STM32MP15x lines 
  • 91 How to go further
  • 92 References
  • 93 Article purpose
  • 94 Peripheral overview
  • 94.1 Features
  • 94.2 Security support 94.2.1 On STM32MP13x lines 94.2.2 On STM32MP15x lines 95 Using the peripheral - associated software
  • 95.1 Boot time
  • 95.2 Runtime
  • 95.2.1 Overview
  • 95.2.2 Software frameworks 95.2.2.1 On STM32MP13x lines 95.2.2.2 On STM32MP15x lines 
  • 95.2.3 Peripheral configuration
  • 95.2.4 Peripheral assignment 95.2.4.1 On STM32MP13x lines 95.2.4.2 On STM32MP15x lines 
  • 96 References
  • 97 Article purpose
  • 98 Peripheral overview
  • 98.1 Features
  • 98.2 Security support 98.2.1 On STM32MP13x lines 98.2.2 On STM32MP15x lines 99 Peripheral usage and associated software
  • 99.1 Boot time
  • 99.2 Runtime
  • 99.2.1 Overview
  • 99.2.2 Software frameworks 99.2.2.1 On STM32MP13x lines 99.2.2.2 On STM32MP15x lines 
  • 99.2.3 Peripheral configuration
  • 99.2.4 Peripheral assignment 99.2.4.1 On STM32MP13x lines 99.2.4.2 On STM32MP15x lines 
  • 100 References
  • 101 Article purpose
  • 102 Peripheral overview
  • 102.1 Features
  • 102.2 Security support 102.2.1 On STM32MP13x lines 102.2.2 On STM32MP15x lines 103 Peripheral usage and associated software
  • 103.1 Boot time
  • 103.2 Runtime
  • 103.2.1 Overview
  • 103.2.2 Software frameworks 103.2.2.1 On STM32MP13x lines 103.2.2.2 On STM32MP15x lines 
  • 103.2.3 Peripheral configuration
  • 103.2.4 Peripheral assignment 103.2.4.1 On STM32MP13x lines 103.2.4.2 On STM32MP15x lines 
  • 104 References
  • 105 Article purpose
  • 106 Peripheral overview
  • 107 Peripheral usage and associated software
  • 107.1 Boot time
  • 107.2 Runtime
  • 107.2.1 Overview
  • 107.2.2 Software frameworks 107.2.2.1 On STM32MP13x lines 107.2.2.2 On STM32MP15x lines 
  • 107.2.3 Peripheral configuration
  • 107.2.4 Peripheral assignment 107.2.4.1 On STM32MP13x lines 107.2.4.2 On STM32MP15x lines 
  • 108 References
  • 109 Peripheral overview
  • 110 Peripheral usage and associated software
  • 110.1 Boot time
  • 110.2 Runtime
  • 110.2.1 Overview
  • 110.2.2 Software frameworks 110.2.2.1 On STM32MP13x lines 110.2.2.2 On STM32MP15x lines 
  • 110.2.3 Peripheral configuration
  • 110.2.4 Peripheral assignment 110.2.4.1 On STM32MP13x lines 110.2.4.2 On STM32MP15x lines 
  • 111 References
  • 112 Article purpose
  • 113 Peripheral overview
  • 114 Peripheral usage and associated software
  • 114.1 Boot time
  • 114.2 Runtime
  • 114.2.1 Overview
  • 114.2.2 Software frameworks 114.2.2.1 On STM32MP13x lines 114.2.2.2 On STM32MP15x lines 
  • 114.2.3 Peripheral configuration
  • 114.2.4 Peripheral assignment 114.2.4.1 On STM32MP13x lines 114.2.4.2 On STM32MP15x lines 
  • 115 How to go further
  • 116 References
  • 117 Article purpose
  • 118 Peripheral overview
  • 118.1 Features
  • 118.2 Security support 118.2.1 On STM32MP13x lines 118.2.2 On STM32MP15x lines 119 Peripheral usage and associated software
  • 119.1 Boot time
  • 119.2 Runtime
  • 119.2.1 Overview
  • 119.2.2 Software frameworks 119.2.2.1 On STM32MP13x lines 119.2.2.2 On STM32MP15x lines 
  • 119.2.3 Peripheral configuration
  • 119.2.4 Peripheral assignment 119.2.4.1 On STM32MP13x lines 119.2.4.2 On STM32MP15x lines 
  • 120 References
  • 121 Article purpose
  • 122 Peripheral overview
  • 122.1 Features
  • 122.2 Security support 122.2.1 On STM32MP13x lines 122.2.2 On STM32MP15x lines 123 Peripheral usage and associated software 123.1 Boot time 123.1.1 On STM32MP13x lines 123.1.2 On STM32MP15x lines 123.2 Runtime 123.2.1 Overview 123.2.1.1 On STM32MP13x lines 123.2.1.2 On STM32MP15x lines 123.2.2 Software frameworks 123.2.2.1 On STM32MP13x lines 123.2.2.2 On STM32MP15x lines 
  • 123.2.3 Peripheral configuration
  • 123.2.4 Peripheral assignment 123.2.4.1 On STM32MP13x lines 123.2.4.2 On STM32MP15x lines 
  • 124 References
  • 125 Article purpose
  • 126 Peripheral overview
  • 127 Peripheral usage and associated software
  • 127.1 Boot time
  • 127.2 Runtime
  • 127.2.1 Overview
  • 127.2.2 Software frameworks 127.2.2.1 On STM32MP13x lines 127.2.2.2 On STM32MP15x lines 
  • 127.2.3 Peripheral configuration
  • 127.2.4 Peripheral assignment 127.2.4.1 On STM32MP13x lines 127.2.4.2 On STM32MP15x lines 
  • 128 How to go further
  • 129 References
  • 130 Article purpose
  • 131 Peripheral overview
  • 132 Peripheral usage and associated software
  • 132.1 Boot time
  • 132.2 Runtime
  • 132.2.1 Overview
  • 132.2.2 Software frameworks 132.2.2.1 On STM32MP13x lines 132.2.2.2 On STM32MP15x lines 
  • 132.2.3 Peripheral configuration
  • 132.2.4 Peripheral assignment 132.2.4.1 On STM32MP13x lines 132.2.4.2 On STM32MP15x lines 
  • 133 Article purpose
  • 134 Peripheral overview
  • 135 Peripheral usage and associated software
  • 135.1 Boot time
  • 135.2 Runtime
  • 135.2.1 Overview
  • 135.2.2 Software frameworks 135.2.2.1 On STM32MP13x lines 135.2.2.2 On STM32MP15x lines 
  • 135.2.3 Peripheral configuration
  • 135.2.4 Peripheral assignment 135.2.4.1 On STM32MP13x lines 135.2.4.2 On STM32MP15x lines 
  • 136 Article purpose
  • 137 Peripheral overview
  • 137.1 Features
  • 137.2 Security support 137.2.1 On STM32MP13x lines 137.2.2 On STM32MP15x lines 138 Peripheral usage and associated software
  • 138.1 Boot time
  • 138.2 Runtime
  • 138.2.1 Overview
  • 138.2.2 Software frameworks 138.2.2.1 On STM32MP13x lines 138.2.2.2 On STM32MP15x lines 
  • 138.2.3 Peripheral configuration
  • 138.2.4 Peripheral assignment 138.2.4.1 On STM32MP13x lines 138.2.4.2 On STM32MP15x lines 
  • 139 How to go further
  • 140 References
  • 141 References
  • 1 Internal peripherals overview[edit]

    The figure below shows all peripherals embedded in STM32MP15 device, grouped per functional domains that are reused in many places of this wiki to structure the articles.

    Several runtime contexts exist on STM32MP15 device[1], corresponding to the different Arm cores and associated security modes:

    •  Arm dual core Cortex-A7 secure  (Trustzone), running a Secure Monitor or Secure OS like OP-TEE
    •  Arm dual core Cortex-A7 non secure , running Linux
    •  Arm Cortex-M4  (non-secure), running STM32Cube


    Some peripherals can be strictly assigned to one runtime context: this is the case for most of the peripherals, like USART or I2C.
    Other ones can be shared between several runtime contexts: this is the case for system peripherals, like PWR or RCC.
    The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

    STM32MP1IPsOverview legend.png

    Both the diagram below and the following summary table (in Internal peripherals assignment chapter below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.


    STGEN SYSCFG RTC EXTI GIC NVIC IWDG IWDG WWDG DMA DMA DMAMUX MDMA SYSRAM DDR via DDR CTRL BKPSRAM MCU SRAM MCU SRAM RETRAM TIM TIM LPTIM GPIO GPIO IPCC HSEM RCC PWR DTS DDRPERFM DBGMCU HDP STM BSEC QUADSPI FMC SDMMC FDCAN ETH SDMMC USBH OTG USBPHYC USART USART USART I2C I2C I2C SPI SPI RNG HASH ETZPC CRYP CRC TZC RNG HASH TAMP CRYP CRC GPU DSI LTDC DCMI CEC VREFBUF DAC DFSDM ADC SPI I2S SPDIFRX SAI
    STM32MP1 internal peripherals overview Template:WarningImageMapOverlay

    2 Internal peripherals assignment[edit]

    Internal peripherals assignment table template

    Information about "ADC internal peripheral" depends on the microprocessor device.

    To manage this diversity and to provide the relevant level of information, several articles have been created. Please browse the one corresponding to the STM32 MPU you use.

    STM32 MPU devices Associated articles
    STM32MP13x STM32MP13 ADC internal peripheral
    STM32MP15x STM32MP15 ADC internal peripheral
    | rowspan="1" | Analog
    | rowspan="1" | DAC
    | DAC
    | 
    | 
    | 
    | Assignment (single choice)
    |-
    
    

    3 Article purpose[edit]

    The purpose of this article is to

    • briefly introduce the DFSDM peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when needed, how to configure the DFSDM peripheral.

    4 Peripheral overview[edit]

    The DFSDM peripheral (Digital Filter for Sigma-Delta Modulator) is used as a generic ADC. It benefits from external analog frontend interfaces and internal digital filters.
    It can be used in various applications[3] such as: audio record with MEMS microphones, energy measurement with STPMS2[4] for electricity meters or motor control...

    4.1 Features[edit]

    The DFSDM peripheral provides several features, among which:

    • Serial or parallel input channels:
      • External analog frontend serial interfaces (SPI, manchester coded single wire interface, clock output), for various sigma-delta modulators
      • Alternative Internal digital parallel interfaces (from internal ADC[5] or memory data stream via DMA[6] or CPU)
    • Digital filters, that offers up to 24-bit final ADC resolution
    • Conversions that can be launched continuously, or using various triggers: by software, TIM[7], LPTIM[8], EXTI[9] or synchronously with DFSDM filter 0
    • Event detectors: analog watchdog high/low thresholds, short-circuit detector, extremes detector
    • Break generation to TIM[7] on analog watchdog or short-circuit detector events
    DFSDM features Number of channels Number of filters
    STM32MP13x lines Warning.png 4 2
    STM32MP15x lines More info.png 8 6

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete features list, and to the software components, introduced below, to know which features are really implemented.

    4.2 Security support[edit]

    The DFSDM is a non-secure peripheral.

    5 Peripheral usage and associated software[edit]

    5.1 Boot time[edit]

    The DFSDM is not used at boot time.

    5.2 Runtime[edit]

    5.2.1 Overview[edit]

    The DFSDM can be allocated to:

    • the Arm® Cortex®-A7 non-secure core to be used under Linux® by the IIO or ALSA framework

    or

    The peripheral assignment chapter describes which peripheral instance can be assigned to which context.

    5.2.2 Software frameworks[edit]

    5.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux Analog DFSDM Linux IIO framework
    Linux ALSA framework
    5.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Analog DFSDM Linux IIO framework
    Linux ALSA framework STM32Cube DFSDM driver

    5.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

    For the Linux kernel configuration, please refer to DFSDM device tree configuration and DFSDM Linux driver articles.

    5.2.4 Peripheral assignment[edit]

    5.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Analog DFSDM DFSDM Assignment (single choice)
    5.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Cortex-M4

    (STM32Cube)
    Analog DFSDM ADC DFSDM ADC Assignment (single choice)

    6 How to go further[edit]

    See:

    • STM32L4 System Digital Filter for SD Modulators interface[3], online DFSDM training with application examples from STMicroelectronics
    • Getting started with sigma-delta digital interface[10], application note from STMicroelectronics

    7 References[edit]

    Information about "VREFBUF internal peripheral" depends on the microprocessor device.

    To manage this diversity and to provide the relevant level of information, several articles have been created. Please browse the one corresponding to the STM32 MPU you use.

    STM32 MPU devices Associated articles
    STM32MP13x STM32MP13 VREFBUF internal peripheral
    STM32MP15x STM32MP15 VREFBUF internal peripheral

    8 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the SAI peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain how to configure the SAI peripheral.

    9 Peripheral overview[edit]

    The SAI (Serial Audio Interface) offers a wide set of audio protocols, such as: I2S standards (LSB or MSB-justified), PCM/DSP, TDM and S/PDIF. The SAI contains two independent audio sub-blocks. Each sub-block has its own clock generator and I/O line controller, and can be configured either as transmitter or receiver.

    9.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list, and to the software components, introduced below, to see which features are implemented.

    9.2 Security support[edit]

    All the SAI instances are non secure peripherals.

    10 Peripheral usage and associated software[edit]

    10.1 Boot time[edit]

    The SAI is not used at boot time.

    10.2 Runtime[edit]

    10.2.1 Overview[edit]

    SAI instances can be allocated to:

    • the Cortex-A7 non-secure for use in Linux with ALSA framework on STM32MP1 Series
    • the Cortex-M4 for use in STM32Cube with STM32Cube SAI driver on STM32MP15x lines More info.png only

    Chapter #Peripheral assignment exposes which instance can be assigned to which context.

    10.2.2 Software frameworks[edit]

    10.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux Audio SAI ALSA framework
    10.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Audio SAI ALSA framework STM32Cube SAI driver

    10.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    When the Arm® Cortex®-A7 core operates in non-secure access mode, the SAI is controlled by the Linux kernel framework. Refer to SAI Linux driver to drive the SAI through Linux kernel ALSA framework. Refer to Soundcard configuration and SAI device tree configuration to configure the SAI through the Linux kernel device tree[1].

    10.2.4 Peripheral assignment[edit]

    10.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Audio SAI SAI1 Analog DAC DAC Assignment (single choice)
    Analog DFSDM DFSDM Assignment (single choice) SAI2
    Analog VREFBUF VREFBUF Assignment (single choice)
    10.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Audio SAI SAI1 Assignment (single choice)
    SAI2 Assignment (single choice)
    SAI3 Assignment (single choice)
    SAI4 Assignment (single choice)

    11 How to go further[edit]

    STM32H7 SAI training [2] introduces the SAI features and applications. The SAI versions in STM32H7 and STM32MP1 Series are very close. In consequence this training is also relevant for STM32MP1 Series. The user should refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for a complete description.

    12 References[edit]

    13 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the SPDIFRX peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain how to configure the SPDFIRX peripheral.

    14 Peripheral overview[edit]

    The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. The SPDIFRX receiver provides two separated paths to retrieve the audio data and the user and channel information.

    14.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list, and to the software components, introduced below, to see which features are implemented.

    14.2 Security support[edit]

    The SPDFIRX is a non secure peripheral.

    15 Peripheral usage and associated software[edit]

    15.1 Boot time[edit]

    The SPDFIRX is not used at boot time.

    15.2 Runtime[edit]

    15.2.1 Overview[edit]

    The SPDIFRX instance can be allocated to:

    Chapter #Peripheral assignment exposes which instance can be assigned to which context.

    15.2.2 Software frameworks[edit]

    15.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux
    Audio SPDIFRX
    ALSA framework
    15.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Audio
    SPDIFRX
    ALSA framework STM32Cube SPDIFRX driver

    15.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    When the Arm® Cortex®-A7 core operates in non-secure access mode, the SPDIFRX is controlled by the Linux kernel framework. Refer to the SPDIFRX Linux driver to drive the SPDIFRX through Linux kernel ALSA framework. Refer to Soundcard configuration and SPDIFRX device tree configuration to configure the SPDIFRX through Linux kernel device tree[1].

    15.2.4 Peripheral assignment[edit]

    15.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.
  • Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Audio SPDIFRX SPDIFRX Assignment (single choice)
    15.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Domain Peripheral Runtime allocation Comment Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Cortex-M4
    (STM32Cube)Audio SPDIFRX SPDIFRX Assignment (single choice)

    16 How to go further[edit]

    The STM32H7 SPDIFRX training [2], introduces the STM32 S/PDIF Receiver interface on the STM32H7. This training also applies to the STM32 MPU SPDIFRX internal peripheral.

    17 References[edit]

    | rowspan="1" | Coprocessor
    | rowspan="1" | IPCC
    | IPCC
    |
    | 
    | 
    | Shared (none or both)
    |-
    
    
    | rowspan="1" | Coprocessor
    | rowspan="1" | HSEM
    | HSEM
    | 
    | 
    | 
    | 
    |-
    
    
    Technical information related to "RTC internal peripheral" depends on the microprocessor device.
    Several articles have been created, one per STM32 MPU device, to manage those differences.
    You can find information corresponding to the STM32 MPU you use, by clicking on on of articles below.
    STM32 MPU devices Associated articles
    STM32MP13x STM32MP13 RTC internal peripheral
    STM32MP15x STM32MP15 RTC internal peripheral

    18 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the STGEN peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how it can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when necessary, how to configure the STGEN peripheral.

    19 Peripheral overview[edit]

    The STGEN peripheral provides the reference clock used by the Arm® Cortex®-A7 generic timer for its counters, including the system tick generation.

    It is clocked by ACLK (the AXI bus clock), so caution is needed when this clock is changed; otherwise the operating system (running on the Cortex-A7) might run with a varying reference clock.

    19.1 Features[edit]

    Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

    19.2 Security support[edit]

    The STGEN is a single-instance peripheral that can be accessed via the two following register sets:

    • STGENC for the control. That is, a secure port (under ETZPC control).
    • STGENR for the read-only access. That is, a non secure port.

    20 Peripheral usage and associated software[edit]

    20.1 Boot time[edit]

    The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chain overview) once the clock tree is set up.

    20.2 Runtime[edit]

    20.2.1 Overview[edit]

    Linux® and OP-TEE use the Arm Cortex-A7 generic timer that gets its counter from the STGEN, but this is transparent at run time.

    Hence there is no runtime allocation decision for this peripheral: both contexts are selected by default.

    20.2.2 Software frameworks[edit]

    20.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment
    OP-TEE Linux
    Core STGEN see comment see comment Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime
    20.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core STGEN see comment see comment Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime

    20.2.3 Peripheral configuration[edit]

    20.2.4 Peripheral assignment[edit]

    20.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core STGEN STGEN
    20.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Domain Peripheral Runtime allocation Comment Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Cortex-M4
    (STM32Cube)Core STGEN STGEN

    21 References[edit]

    Technical information related to "SYSCFG internal peripheral" depends on the microprocessor device.
    Several articles have been created, one per STM32 MPU device, to manage those differences.
    You can find information corresponding to the STM32 MPU you use, by clicking on one of the articles below.
    STM32 MPU devices Associated articles
    STM32MP13x STM32MP13 SYSCFG internal peripheral
    STM32MP15x STM32MP15 SYSCFG internal peripheral

    22 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the DMA peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when necessary, how to configure the DMA peripheral.

    23 Peripheral overview[edit]

    The DMA peripheral is used to perform direct accesses from/to a device or a memory. Each DMA instance supports 8 channels. The selection of the device connected to each DMA channel and controlling the DMA transfers is done via the DMAMUX.

    Note: Directly accessing DDR from the DMA is not recommended for high-bandwith or latency-critical transfers. This means that DMA transfers configured by the Arm® Cortex®-A7 operating system, that usually target buffers in external memory, require a hardware mechanism to chain the DMA and a MDMA channel in order to achieve the following flow:

    DDR<-> MDMA <-> MCU SRAM <-> DMA <-> device

    This feature was already present on STM32H7 microcontroller Series. It is documented in application note AN5001[1].

    23.1 Features[edit]

    Refer to the STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

    23.2 Security support[edit]

    23.2.1 On STM32MP13x lines Warning.png[edit]

    DMA1 and DMA2 instances are non-secure peripherals. DMA3 is a secure peripheral.

    23.2.2 On STM32MP15x lines More info.png[edit]

    DMA1 and DMA2 instances are non-secure peripherals.

    24 Peripheral usage and associated software[edit]

    24.1 Boot time[edit]

    The DMA is not used at boot time.

    24.2 Runtime[edit]

    24.2.1 Overview[edit]

    24.2.1.1 On STM32MP13x lines Warning.png[edit]

    DMA1 and DMA2 can be assigned to the Arm® Cortex®-A7 non-secure context to be controlled in Linux® by the dmaengine framework.
    DMA3 can be assigned to the Arm® Cortex®-A7 secure context, to be controlled by a DMA OP-TEE driver, not supported yet by OpenSTLinux.

    24.2.1.2 On STM32MP15x lines More info.png[edit]

    Each DMA instance can be allocated to:

    • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the dmaengine framework

    or

    • the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by the DMA HAL driver

    24.2.2 Software frameworks[edit]

    24.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux Core/DMA DMA OP-TEE DMA driver Linux dmaengine framework
    24.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core/DMA DMA Linux dmaengine framework STM32Cube DMA driver

    24.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    24.2.4 Peripheral assignment[edit]

    24.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/DMA DMA DMA1 Assignment (single choice) DMA2 Assignment (single choice) DMA3 Assignment (single choice)
    24.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Coprocessor IPCC IPCC Shared (none or both)
    Coprocessor HSEM HSEM
    Core RTC RTC RTC is mandatory to resynchronize STGEN after exiting low-power modes.
    Core STGEN STGEN
    Core SYSCFG SYSCFG
    Core/DMA DMA DMA1 Assignment (single choice)
    DMA2 Assignment (single choice)

    25 References[edit]

    26 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the DMAMUX peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when necessary, how to configure the DMAMUX peripheral.

    27 Peripheral overview[edit]

    The DMAMUX peripheral is used to perform requestor line (or device controller) selection for each channel from DMA instances:

    • In STM32MP13x lines Warning.png there is a first DMAMUX instance to cover both DMA1 and DMA2, and second DMAMUX instance to cover DMA3.
    • In STM32MP15x lines More info.png there is a single DMAMUX instance to cover both DMA1 and DMA2.

    27.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list and to the software components, introduced below, to see which features are implemented.

    27.2 Security support[edit]

    27.2.1 On STM32MP13x lines Warning.png[edit]

    The DMAMUX1 is a non-secure peripheral. The DMAMUX2 is a secure peripheral.

    27.2.2 On STM32MP15x lines More info.png[edit]

    The DMAMUX is a non secure peripheral.

    28 Peripheral usage and associated software[edit]

    28.1 Boot time[edit]

    The DMAMUX is not used at boot time.

    28.2 Runtime[edit]

    28.2.1 Overview[edit]

    28.2.1.1 On STM32MP13x lines Warning.png[edit]

    The DMAMUX1 manages DMA1 and DMA2 requestor line selection, so it can be assigned to the Arm® Cortex®-A7 non-secure context to be controlled in Linux® by the dmaengine framework. The DMAMUX2 manages DMA3 requestor line selection, so it can be assigned to the Arm® Cortex®-A7 secure context to be controlled by a DMAMUX OP-TEE driver, not supported yet by OpenSTLinux.

    28.2.1.2 On STM32MP15x lines More info.png[edit]

    The DMAMUX manages DMA1 and DMA2 requestor line selection via different registers so it is possible to concurrently access to DMAMUX from Cortex®-A7 non-secure and Cortex®-M4 contexts, as far as each core is only configuring the requestor lines for the DMA instances (DMA1 and/or DMA2) assigned to itself.

    Finally, DMAMUX can be allocated to:

    • the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the dmaengine framework

    or

    • the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by the DMA HAL driver

    28.2.2 Software frameworks[edit]

    28.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux
    Core/DMA DMAMUX
    OP-TEE
    DMAMUX
    driver
    Linux dmaengine framework
    28.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core/DMA DMAMUX Linux dmaengine framework STM32Cube DMAMUX driver

    28.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    28.2.4 Peripheral assignment[edit]

    28.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.
  • Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/DMA DMAMUX DMAMUX1 Assignment (single choice) DMAMUX2 Assignment (single choice)
    28.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/DMA DMAMUX DMAMUX Shareable (multiple choices supported)

    29 Article purpose[edit]

    The purpose of this article is to:

    • briefly introduce the MDMA peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when necessary, how to configure the MDMA peripheral.

    30 Peripheral overview[edit]

    The MDMA is used to perform high-speed data transfers between memory and memory or between peripherals and memory. The MDMA controller offers 32 channels. The selection of the device connected to each channel and controlling DMA transfers is done in MDMA peripheral.

    Among all the requestor lines described in the reference manual (accessible via the following paragraph), DMA channels are the only lines that allow to perform transfers with chained DMA and MDMA (refer to DMA internal peripheral article). As a result, when a device is not connected to the MDMA, it is anyway possible to operate in DMA mode via the DMA controller and chain DMA and MDMA.

    30.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

    30.2 Security support[edit]

    The MDMA is a secure peripheral. This means that it performs each transfer in the context of the master that requested it:

    • a transfer requested by the Arm® Cortex®-A7 non-secure core propagates non-secure accesses to the targeted device and/or memory.
    • a transfer requested by Arm Cortex-A7 secure core propagates secure accesses to the targeted device and/or memory.

    31 Peripheral usage and associated software[edit]

    31.1 Boot time[edit]

    The MDMA is used at boot time by the FMC.

    31.2 Runtime[edit]

    31.2.1 Overview[edit]

    As stated in the 'Security support' chapter above, the MDMA is a secure peripheral. This means that its channels have to be allocated to:

    • the Arm Cortex-A7 non-secure core to be controlled in Linux® by the dmaengine framework

    and

    • the Arm Cortex-A7 secure core to be controlled by a MDMA OP-TEE driver, not supported yet by OpenSTLinux.

    STM32CubeMX allows to distinguish between non-secure and secure channels, among all the available channels.

    On STM32MP15x lines More info.png, the MDMA is visible from the Arm Cortex-M4 core. However, it is not supported in this context by STM32MPU Embedded Software distribution.

    31.2.2 Software frameworks[edit]

    31.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux
    Core/DMA MDMA
    OP-TEE
    MDMA
    driver
    Linux dmaengine framework
    31.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core/DMA MDMA OP-TEE MDMA driver Linux dmaengine framework

    31.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    31.2.4 Peripheral assignment[edit]

    31.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.
  • Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/DMA MDMA MDMA Shareable (multiple choices supported)
    31.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/DMA MDMA MDMA Shareable (multiple choices supported)

    32 Peripheral overview[edit]

    The EXTI peripheral is used to get an interrupt when a GPIO is toggling. It can also wake up the system from Stop low power mode, by means of the PWR internal peripheral when a wake up event occurs, before (eventualy - see the note below) propagating an interrupt to the client processor (Cortex-A7 GIC or Cortex-M4 NVIC in case of STM32MP15). The wake up events can be internal (from other IPs clocked by the LSE, LSI or HSI from RCC), or external (from GPIO).
    Notice that:
    • Up to 16 GPIO pins can be configured as external interrupts: for each index between 0 and 15, one EXTI can be selected among all banks (EXTI<index> = GPIO<one_bank><index>).
    • On STM32MP13x lines Warning.png: The 16 GPIO and one internal peripheral events ( AVD/PVD), can generate interrupts connected to the GIC. All the other internal peripheral events can wake up the system, but the EXTI does not generate any interrupt to the GIC; in such cases, another peripheral interrupt has to be used as a trigger via the GIC.
    • On STM32MP15x lines More info.png: The 16 GPIO and 5 internal peripheral events (AVD/PVD, CPU1 SEV, CPU2 SEV, WWDG1 reset, CPU2 SYSRESETREQ) can generate interrupts connected to the GIC and NVIC. All the other internal peripheral events can wake up the system, but the EXTI does not generate any interrupt to the GIC or NVIC for them; in such cases, another peripheral interrupt has to be used as a trigger via the GIC or NVIC.

    32.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list, and to the software components, introduced below, to see which features are implemented.

    32.2 Security support[edit]

    The EXTI is a secure peripheral. By default, at reset, all EXTI wake up events are non-secure.

    33 Peripheral usage and associated software[edit]

    33.1 Boot time[edit]

    The EXTI is not used by the boot chain, but is configured during Linux initialization.

    33.1.1 On STM32MP15x lines More info.png[edit]

    Since wake-up event configuration is done via register bit-field reads and writes, concurrent accesses from Linux and the coprocessor are not possible at boot time:

    • Linux configures all EXTI events during their respective consumer driver probing
    • The coprocessor uses the resource management mechanisms to request and configure the EXTI events it needs.

    33.2 Runtime[edit]

    33.2.1 Overview[edit]

    33.2.1.1 On STM32MP13x lines Warning.png[edit]

    The EXTI is used by:

    • the Cortex-A7 non-secure with Linux interrupts framework
    • the Cortex-A7 secure with OP-TEE EXTI driver
    33.2.1.2 On STM32MP15x lines More info.png[edit]

    The EXTI is a shared peripheral, that can be used by:

    33.2.2 Software frameworks[edit]

    33.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux Core/
    Interrupts EXTI
    OP-TEE
    EXTI
    driver
    Linux interrupt framework
    33.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core/Interrupts EXTI Linux interrupt framework STM32Cube EXTI driver

    33.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

    33.2.4 Peripheral assignment[edit]

    33.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/Interrupts EXTI EXTI
    33.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/Interrupts EXTI EXTI Shared
    Info white.png Information
    The EXTI peripheral is not listed in STM32CubeMX peripherals list because its configuration is partly embedded in the Device tree (for all internal EXTI sources, coming from peripherals with wake up capabilities) and completed with the GPIO configuration that comes from STM32CubeMX pinout view

    34 Article purpose[edit]

    The purpose of this article is to

    • briefly introduce the GIC peripheral (generic interrupt controller) and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain, when needed, how to configure the GIC peripheral.

    35 Peripheral overview[edit]

    The GIC peripheral is the Arm® Cortex®-A7 interrupt controller.
    It is consequently not accessible from the Arm® Cortex®-M4 core on STM32MP15x lines More info.png.

    35.1 Features[edit]

    Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

    35.2 Security support[edit]

    The GIC is a secure peripheral (under ETZPC control).

    36 Peripheral usage and associated software[edit]

    36.1 Boot time[edit]

    The GIC is configured by the FSBL (see Boot chain overview), mainly to define the routing of each interrupt to the secure or non-secure context at runtime.

    36.2 Runtime[edit]

    36.2.1 Overview[edit]

    The GIC is shared between:

    • the Arm® Cortex®-A7 secure core to be used under OP-TEE with the GIC OP-TEE driver (or TF-A secure monitor if the OP-TEE is not present)
    • the Arm® Cortex®-A7 non-secure core to be used under Linux® with the interrupts framework

    36.2.2 Software frameworks[edit]

    36.2.2.1 On STM32MP13x lines Warning.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux
    Core/Interrupts GIC
    OP-TEE
    GIC
    driver
    Linux interrupt framework
    36.2.2.2 On STM32MP15x lines More info.png[edit]
    Domain Peripheral Software components Comment OP-TEE Linux STM32Cube Core/Interrupts GIC OP-TEE GIC driver Linux interrupt framework

    36.2.3 Peripheral configuration[edit]

    The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

    36.2.4 Peripheral assignment[edit]

    36.2.4.1 On STM32MP13x lines Warning.png[edit]

    Click on the right to expand the legend...

    STM32MP13IPsOverview.png

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/Interrupts GIC GIC
    36.2.4.2 On STM32MP15x lines More info.png[edit]

    Click on the right to expand the legend...

    STM32MP15 internal peripherals

    Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

    • means that the peripheral can be assigned () to the given runtime context.
    • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
    • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

    Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
    The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

    Cortex-M4
    (STM32Cube)
    Domain Peripheral Runtime allocation Comment
    Instance Cortex-A7
    secure
    (OP-TEE)
    Cortex-A7
    non-secure
    (Linux)
    Core/Interrupts GIC GIC
    | rowspan="1" | Core/Interrupts
    | rowspan="1" | NVIC
    | NVIC
    | 
    |
    | 
    |
    |-
    
    

    37 Article purpose[edit]

    The purpose of this article is to

    • briefly introduce the GPIO peripheral and its main features
    • indicate the level of security supported by this hardware block
    • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
    • explain how to configure the GPIO peripheral.

    38 Peripheral overview[edit]

    The GPIO peripheral is used to configure the device IO ports, also called pins or pads.
    On STM32MP13x lines Warning.png, each GPIO instance controls 16 pins (for GPIOA to GPIOG), 15 pins (for GPIOH) or 8 pins (for GPIOI).
    On STM32MP15x lines More info.png, each GPIO instance controls 16 pins (for GPIOA to GPIOJ) or 8 pins (for GPIOK and GPIOZ).
    Every IO port implements the logic shown in the image below, taken from STM32MP15 reference manuals (and the same exists in STM32MP13 reference manuals):
  • The IO pin (on the right) is the physical connection to a chip external ball, soldered on the PCB. The link between each GPIO pin and each ball of the package is given in the datasheet (Datasheets for STM32MP13x lines Warning.png and Datasheets for STM32MP15x lines More info.png).
  • The Read and Write accesses allow the processor (Arm® Cortex®-A7 for for STM32MP1 Series or Arm® Cortex®-M4 for for STM32MP15x lines More info.png) to configure the peripheral, control the IO pin and get its status.
  • Alternate function (AF) links allow to connect the IO port to an internal peripheral digital line. In such a case, the IO direction is given by the line purpose: for instance, UART transmit line (TX) is an output.
  • Analog links allow to connect the IO port to an internal peripheral analog line. In such a case, the IO direction is given by the line purpose: for instance, ADC input line is an input.

    IO port.png

    Note: