Difference between revisions of "STM32MP15 ETZPC internal peripheral"

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Applicable for STM32MP15x lines

1 Article purpose[edit]

The purpose of this article is to:

  • briefly introduce the ETZPC peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how it can be allocated to the runtime contexts and linked to the corresponding software components
  • explain , when necessary, how to configure the ETZPC peripheral if necessary.

2 Peripheral overview[edit]

The ETZPC peripheral is used to configure TrustZone security in a SoC having STM32 MPU device. That STM32 MPU device has bus masters and slaves with programmable-security attributes (securable resources) such as:

  • on-chip RAM/ROM with programmable secure region size
  • AHB and APB peripherals to be made secure
  • AHB masters to be granted secure rights

The ETZPC peripheral also allows peripheral isolation. With MCU isolation, some peripherals can be assigned to Cortex-M4 context execution only. Those peripherals will not be accessible for Cortex-A7 contexts (secure and non-secure).

2.1 Features[edit]

Refer to the STM32MP15 reference manuals for the complete list of features, and . Refer also to the software components, introduced below, to see which features are implemented.

2.2 Security support[edit]

The ETZPC is a secure peripheral.

3 Peripheral usage and associated software[edit]

3.1 Boot time[edit]

The ETZPC is configured at boot time to setup the platform security.

3.2 Runtime[edit]

3.2.1 Overview[edit]

The ETZPC is a system peripheral and is controlled by the Arm® Cortex®-A7 secure.

3.2.2 Software frameworks[edit]

Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Security ETZPC TF-A(BL32)
or
OP-TEE ETZPC driver
Read/Write access
U-Boot
Read only access
Resource Manager Utility
Read only access
Configuration made by A7 secure.
U-Boot updates the Linux
device tree.

3.2.3 Peripheral configuration[edit]

The configuration is applied by the firmware running in a secure context.
This configuration is done in TF-A(BL32) or OP-TEE, through device tree (see .
Refer to ETZPC device tree configuration).

3.2.4 Peripheral assignment[edit]

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned () to the given runtime context.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Security ETZPC ETZPC

4 How to go further[edit]

The ETZPC is an STMicroelectronics extension of the Arm® peripheral: TrustZone Protection Controller[1].

5 References[edit]


. .

<noinclude>{{ApplicableFor
|MPUs list=STM32MP15x
|MPUs checklist=STM32MP13x, STM32MP15x
}}</noinclude>

==Article purpose==
The purpose of this article is to:
* briefly introduce the ETZPC peripheral and its main features
* indicate the level of security supported by this hardware block
* explain how it can be allocated to the runtime contexts and linked to the corresponding software components
* explain, when necessary,  how to configure the ETZPC peripheral if necessary.

==Peripheral overview==
The ETZPC peripheral is used to configure TrustZone security in a SoC having STM32 MPU device. That STM32 MPU device has bus masters and slaves with programmable-security attributes (securable resources) such as:
* on-chip RAM/ROM with programmable secure region size
* AHB and APB peripherals to be made secure
* AHB masters to be granted secure rights
The ETZPC peripheral also allows peripheral isolation. With MCU isolation, some peripherals can be assigned to Cortex-M4 context execution only. Those peripherals will not be accessible for Cortex-A7 contexts (secure and non-secure).

===Features===
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and . Refer also to the software components, introduced below, to see which features are implemented.

===Security support===
The ETZPC is a '''secure''' peripheral.

==Peripheral usage and associated software==
===Boot time===
The ETZPC is configured at boot time to setup the platform security.

===Runtime===

====Overview====
The ETZPC is a system peripheral and is controlled by the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure.

====Software frameworks====
{{:STM32MP15_internal_peripherals_software_table_template}}
 | Security
 | [[STM32MP15 ETZPC internal peripheral|ETZPC]]
 | [[TF-A_overview#BL32|TF-A(BL32)]] <br>or<br> [[OP-TEE_overview|OP-TEE ETZPC driver]]<br> Read/Write access
 | [[U-Boot_overview|U-Boot]]<br> Read only access
 | [[Resource_manager_for_coprocessing|Resource Manager Utility]]<br> Read only access
 | Configuration made by A7 secure.<br>[[U-Boot_overview|U-Boot]] updates the Linux<br> [[Device_tree|device tree]].
 |-
 |}

====Peripheral configuration====
The configuration is applied by the firmware running in a secure context.

<br>
This configuration is done in [[TF-A_overview#BL32|TF-A(BL32)]] or [[OP-TEE_overview|OP-TEE]], through device tree (see . <br>Refer to [[ETZPC device tree configuration]]).

====Peripheral assignment====
{{:STM32MP15_internal_peripherals_assignment_table_template}}<onlyinclude>

 | rowspan="1" | Security
 | rowspan="1" | [[STM32MP15 ETZPC internal peripheral|ETZPC]]
 | ETZPC
 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 | <span title="system peripheral" style="font-size:21px"></span>

 | 
 |-</onlyinclude>

 |}

==How to go further==
The ETZPC is an STMicroelectronics extension of the Arm<sup>&reg;</sup> peripheral: TrustZone Protection Controller<ref>http://infocenter.arm.com/help/topic/com.arm.doc.dto0015a/DTO0015_primecell_infrastructure_amba3_tzpc_bp147_to.pdf</ref>.


==References==<references/>

<noinclude>

{{ArticleBasedOnModel| Internal peripheral article model}}
[[Category:Security peripherals|ETZPC internal peripheral STM32MP15 ]]
.
{{PublicationRequestId | 24679| 2022-09-26}}.</noinclude>
(12 intermediate revisions by 2 users not shown)
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* indicate the level of security supported by this hardware block
 
* indicate the level of security supported by this hardware block
 
* explain how it can be allocated to the runtime contexts and linked to the corresponding software components
 
* explain how it can be allocated to the runtime contexts and linked to the corresponding software components
* explain, when necessary, how to configure the ETZPC peripheral.
+
* explain how to configure the ETZPC peripheral if necessary.
   
 
==Peripheral overview==
 
==Peripheral overview==
The ETZPC peripheral is used to configure TrustZone security in a SoC having bus masters and slaves with programmable-security attributes (securable resources) such as:
+
The ETZPC peripheral is used to configure TrustZone security in a STM32 MPU device. That STM32 MPU device has bus masters and slaves with programmable-security attributes (securable resources) such as:
 
* on-chip RAM/ROM with programmable secure region size
 
* on-chip RAM/ROM with programmable secure region size
 
* AHB and APB peripherals to be made secure
 
* AHB and APB peripherals to be made secure
Line 18: Line 18:
   
 
===Features===
 
===Features===
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to see which features are implemented.
+
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features. Refer also to the software components, introduced below, to see which features are implemented.
   
 
===Security support===
 
===Security support===
Line 36: Line 36:
 
  | Security
 
  | Security
 
  | [[STM32MP15 ETZPC internal peripheral|ETZPC]]
 
  | [[STM32MP15 ETZPC internal peripheral|ETZPC]]
  | [[TF-A_overview#BL32|TF-A(BL32)]] or [[OP-TEE_overview|OP-TEE ETZPC driver]] Read/Write access
+
  | [[TF-A_overview#BL32|TF-A(BL32)]] <br>or<br> [[OP-TEE_overview|OP-TEE ETZPC driver]]<br> Read/Write access
 
  | [[U-Boot_overview|U-Boot]]<br> Read only access
 
  | [[U-Boot_overview|U-Boot]]<br> Read only access
  | [[Resource_manager_for_coprocessing|Resource Manager Utility]] Read only access
+
  | [[Resource_manager_for_coprocessing|Resource Manager Utility]]<br> Read only access
  | Configuration made by A7 secure.<br>[[U-Boot_overview|U-Boot]] updates the Linux [[Device_tree|device tree]].
+
  | Configuration made by A7 secure.<br>[[U-Boot_overview|U-Boot]] updates the Linux<br> [[Device_tree|device tree]].
 
  |-
 
  |-
 
  |}
 
  |}
   
 
====Peripheral configuration====
 
====Peripheral configuration====
The configuration is applied by the firmware running in a secure context.
+
The configuration is applied by the firmware running in a secure context.<br>
 
+
This configuration is done in [[TF-A_overview#BL32|TF-A(BL32)]] or [[OP-TEE_overview|OP-TEE]], through device tree. <br>Refer to [[ETZPC device tree configuration]].
This configuration is done in [[TF-A_overview#BL32|TF-A(BL32)]] or [[OP-TEE_overview|OP-TEE]], through device tree (see [[ETZPC device tree configuration]]).
 
   
 
====Peripheral assignment====
 
====Peripheral assignment====
Line 63: Line 62:
   
 
==How to go further==
 
==How to go further==
The ETZPC is an STMicroelectronics extension of the Arm<sup>&reg;</sup> peripheral: TrustZone Protection Controller<ref>http://infocenter.arm.com/help/topic/com.arm.doc.dto0015a/DTO0015_primecell_infrastructure_amba3_tzpc_bp147_to.pdf</ref>
+
The ETZPC is an STMicroelectronics extension of the Arm<sup>&reg;</sup> peripheral: TrustZone Protection Controller<ref>http://infocenter.arm.com/help/topic/com.arm.doc.dto0015a/DTO0015_primecell_infrastructure_amba3_tzpc_bp147_to.pdf</ref>.
   
 
==References==
 
==References==
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<noinclude>
 
<noinclude>
 
{{ArticleBasedOnModel| Internal peripheral article model}}
 
{{ArticleBasedOnModel| Internal peripheral article model}}
[[Category:Security peripherals|ETZPC internal peripheral STM32MP15 ]]
+
[[Category:Security peripherals|ETZPC internal peripheral STM32MP15 ]].
  +
{{PublicationRequestId | 24679| 2022-09-26}}.
 
</noinclude>
 
</noinclude>