Difference between revisions of "STM32MP15 DMA"

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1 Article purpose[edit]

The purpose of this article is to explain STM32M1 DMA topology and the associated configurations recommended by ST.

2 STM32MP1 DMA topology[edit]

STM32MP1 owns 3 DMA instances:

  • 1 MDMA internal peripheral dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
  • 2 DMA internal peripheral dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a DMAMUX internal peripheral in charge of routing internal peripheral requests to DMA channels.


The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.


For more information about DMA and MDMA capabilities and internal peripherals associated to the different DMA instances, please refer to STM32MP15 reference manuals.

Info.png Transfers between internal peripherals and DDR are possible but not recommended for high-bandwith or latency-critical transfers

3 ST Recommandations[edit]

3.1 For Cortex-M4 execution context[edit]

Cortex-M4 access by default internal SRAM for code and data.
In this context, DMA transfers will operate only between peripheral and internal SRAM.
That's why ST recommends to dedicate one DMA internal peripheral to Cortex-M4.

3.2 For Cortex-A7 secure execution context[edit]

Cortex-A7 secure firmware is located in SYSRAM (both code and data). As internal peripherals and SRAM associated to Cortex-A7 secure context are defined "secure", DMA channel used in this context should support secure accesses. In this context, DMA transfers will operate in secure mode and only between peripheral and internal SRAM.

3.3 Cortex-A7 non-secure execution context[edit]

Cortex-A7 non-secure firmware is mainly located in external memories (DDR). In consequence, DMA transfers will operate between peripherals and DDR. But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described STM32MP1 DMA topology. To easy the selection, the following table sums up possible choices for each peripheral and highlight recommended configuration.

4 ST reference boards default configuration[edit]

<noinclude>

{{ArticleMainWriter|GeraldB}}
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19}}__FORCETOC__

== Article purpose ==
The purpose of this article is to explain STM32M1 DMA topology and the associated configurations recommended by ST.

== STM32MP1 DMA topology==
STM32MP1 owns 3 DMA instances:
* 1 [[MDMA internal peripheral]] dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
* 2 [[DMA internal peripheral]] dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a [[DMAMUX internal peripheral]] in charge of routing internal peripheral requests to DMA channels. <br/>
<br/>

The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.

For more information about DMA and MDMA capabilities and internal peripherals associated to the different DMA instances, please refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].

{{Info| Transfers between internal peripherals and DDR are possible but not recommended for high-bandwith or latency-critical transfers}}

== ST Recommandations==
=== For Cortex-M4 execution context===
Cortex-M4 access by default internal SRAM for code and data.<br/>

In this context, DMA transfers will operate only between peripheral and internal SRAM.<br/>

That's why ST recommends to dedicate one [[DMA internal peripheral]] to Cortex-M4.<br/>


=== For Cortex-A7 secure execution context===
Cortex-A7 secure firmware is located in SYSRAM (both code and data). As internal peripherals and SRAM associated to Cortex-A7 secure context are defined "secure", DMA channel used in this context should support secure accesses.
In this context, DMA transfers will operate in secure mode and only between peripheral and internal SRAM.

=== Cortex-A7 non-secure execution context===
Cortex-A7 non-secure firmware is mainly located in external memories (DDR). In consequence, DMA transfers will operate between peripherals and DDR.
But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described [[#STM32MP1 DMA topology|STM32MP1 DMA topology]].
To easy the selection, the following table sums up possible choices for each peripheral and highlight recommended configuration.

==ST reference boards default configuration==
<noinclude>
[[Category:STM32MP15 platform configuration|5]]</noinclude>

{{UnderConstruction}}
(One intermediate revision by the same user not shown)
Line 1: Line 1:
  +
__FORCETOC__
  +
  +
== Article purpose ==
  +
The purpose of this article is to explain STM32M1 DMA topology and the associated configurations recommended by ST.
  +
  +
== STM32MP1 DMA topology==
  +
STM32MP1 owns 3 DMA instances:
  +
* 1 [[MDMA internal peripheral]] dedicated to transfers between some internal peripherals and external memories (DDR) and between internal and external memories.
  +
* 2 [[DMA internal peripheral]] dedicated to transfers between internal peripherals and internal SRAM. These two DMA instances are coupled with a [[DMAMUX internal peripheral]] in charge of routing internal peripheral requests to DMA channels. <br/>
  +
<br/>
  +
The following figures show the different DMA configuration available on STM32MP1 and the associated request and data connections.
  +
  +
  +
For more information about DMA and MDMA capabilities and internal peripherals associated to the different DMA instances, please refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]].
  +
  +
{{Info| Transfers between internal peripherals and DDR are possible but not recommended for high-bandwith or latency-critical transfers}}
  +
  +
== ST Recommandations==
  +
=== For Cortex-M4 execution context===
  +
Cortex-M4 access by default internal SRAM for code and data.<br/>
  +
In this context, DMA transfers will operate only between peripheral and internal SRAM.<br/>
  +
That's why ST recommends to dedicate one [[DMA internal peripheral]] to Cortex-M4.<br/>
  +
  +
=== For Cortex-A7 secure execution context===
  +
Cortex-A7 secure firmware is located in SYSRAM (both code and data). As internal peripherals and SRAM associated to Cortex-A7 secure context are defined "secure", DMA channel used in this context should support secure accesses.
  +
In this context, DMA transfers will operate in secure mode and only between peripheral and internal SRAM.
  +
  +
=== Cortex-A7 non-secure execution context===
  +
Cortex-A7 non-secure firmware is mainly located in external memories (DDR). In consequence, DMA transfers will operate between peripherals and DDR.
  +
But as the different internal peripherals don't have the same requirements in term of bandwidth, real time and flow control, customer will have to use one of the three DMA configuration described [[#STM32MP1 DMA topology|STM32MP1 DMA topology]].
  +
To easy the selection, the following table sums up possible choices for each peripheral and highlight recommended configuration.
  +
  +
==ST reference boards default configuration==
  +
 
<noinclude>
 
<noinclude>
{{ArticleMainWriter|GeraldB}}
 
{{ArticleApprovedVersion | Jean-ChristopheT | Nobody | No previous approved version | Automatic approval (article under construction) | 19Feb’19}}
 
 
[[Category:STM32MP15 platform configuration|5]]
 
[[Category:STM32MP15 platform configuration|5]]
 
</noinclude>
 
</noinclude>
{{UnderConstruction}}
 

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